View PIC16CR76IL_647602.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2007 microchip technology inc. ds21993c pic16cr7x data sheet 28/40-pin, 8-bit cmos rom microcontrollers
ds21993c-page ii ? 2007 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2007 microchip technology inc. ds21993c-page 1 pic16cr7x devices included in this data sheet: high-performance risc cpu: ? high-performance risc cpu ? only 35 single-word instructions to learn ? all single-cycle instructions except for program branches which are two-cycle ? operating speed: dc ? 20 mhz clock input dc ? 200 ns instruction cycle ? up to 8k x 14 words of rom program memory, up to 368 x 8 bytes of data memory (ram) ? function compatible to the pic16f73/74/76/77 ? pinout compatible to the pic16f873/874/876/877 ? interrupt capability (up to 12 sources) ? eight-level deep hardware stack ? direct, indirect and relative addressing modes ? processor read access to program memory special microcontroller features: ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? power-saving sleep mode ? selectable oscillator options peripheral features: ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? two capture, compare, pwm modules: - capture is 16-bit, max. resolution is 12.5 ns - compare is 16-bit, max. resolution is 200 ns - pwm max. resolution is 10-bit ? 8-bit, up to 8-channel analog-to-digital converter ? synchronous serial port (ssp) with spi (master mode) and i 2 c ? (slave) ? universal synchronous asynchronous receiver transmitter (usart/sci) ? parallel slave port (psp), 8-bits wide with external rd , wr and cs controls (40/44-pin only) ? brown-out detection circuitry for brown-out reset (bor) cmos technology: ? low-power, high-speed cmos rom technology ? fully static design ? wide operating voltage range: 2.0v to 5.5v ? high sink/source current: 25 ma ? industrial temperature range ? low power consumption: - < 2 ma typical @ 5v, 4 mhz ? tbd -20 a typical @ 3v, 32 khz ? tbd -< 1 a typical standby current ? tbd ? pic16cr73 ? pic16cr74 ? pic16cr76 ? pic16cr77 device program memory (# single word instructions) data sram (bytes) i/o interrupts 8-bit a/d (ch) ccp (pwm) ssp usart timers 8/16-bit spi (master) i 2 c? (slave) pic16cr73 4096 192 22 11 5 2 yes yes yes 2 / 1 pic16cr74 4096 192 33 12 8 2 yes yes yes 2 / 1 pic16cr76 8192 368 22 11 5 2 yes yes yes 2 / 1 pic16cr77 8192 368 33 12 8 2 yes yes yes 2 / 1 28/40-pin, 8-bit cmos rom microcontrollers
pic16cr7x ds21993c-page 2 ? 2007 microchip technology inc. pin diagrams pic16cr76/73 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda pdip, soic, ssop rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss re0/an5/rd re1/an6/wr re2/an7/cs v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16cr77/74 pdip 2 3 4 5 6 1 7 mclr ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss 15 16 17 18 19 20 21 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl 23 24 25 26 27 28 22 rb7 rb6 rb5 rb4 rb3 rb2 rb1 10 11 8 912 13 14 qfn pic16cr73 pic16cr76
? 2007 microchip technology inc. ds21993c-page 3 pic16cr7x pin diagrams (continued) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 8 7 6 5 4 3 2 1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 pic16cr77 ra4/t0cki ra5/an4/ss re0/an5/rd osc1/clkin osc2/clkout rc0/t1oso/t1ck1 nc re1/an6/wr re2/an7/cs v dd v ss rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr nc rb7 rb6 rb5 rb4 nc nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic16cr77 37 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr nc rb7 rb6 rb5 rb4 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/an7/cs re1/an6/wr re0/an5/rd ra5/an4/ss ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 plcc tqfp pic16cr74 pic16cr74
pic16cr7x ds21993c-page 4 ? 2007 microchip technology inc. table of contents device overview ............................................................................................................... .................................................................... 5 memory organization ........................................................................................................... ............................................................... 13 reading program memory ......................................................................................................... ......................................................... 29 i/o ports ..................................................................................................................... ......................................................................... 31 timer0 module ................................................................................................................. ................................................................... 43 timer1 module ................................................................................................................. ................................................................... 47 timer2 module ................................................................................................................. ................................................................... 51 capture/compare/pwm modules .................................................................................................... ................................................... 53 synchronous serial port (ssp) module .......................................................................................... .................................................... 59 universal synchronous asynchronous receiver transmitter (usart) ............................................................... .............................. 69 analog-to-digital converter (a/d) module ...................................................................................... ..................................................... 83 special features of the cpu ................................................................................................... ............................................................ 89 instruction set summary ....................................................................................................... ............................................................ 105 development support ........................................................................................................... ............................................................ 113 electrical characteristics .................................................................................................... ............................................................... 117 dc and ac characteristics graphs and tables ................................................................................... ............................................. 139 packaging information ......................................................................................................... ............................................................. 149 appendix a: revision history ................................................................................................. .......................................................... 159 appendix b: device differences ................................................................................................ ........................................................ 159 appendix c: conversion considerations ......................................................................................... ................................................. 160 the microchip web site ........................................................................................................ ............................................................ 167 customer change notification service .......................................................................................... ................................................... 167 customer support .............................................................................................................. ............................................................... 167 reader response ............................................................................................................... .............................................................. 168 product identification system ................................................................................................. ........................................................... 169 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2007 microchip technology inc. ds21993c-page 5 pic16cr7x 1.0 device overview this document contains device specific information about the following devices: ? dstemp ? dstemp ? dstemp ? dstemp pic16cr73/76 devices are available only in 28-pin packages, while pic16cr74/77 devices are available in 40-pin and 44-pin packages. all devices in the pic16cr7x family share common architecture, with the following differences: ? the dstemp and dstemp have one-half of the total on-chip memory of the dstemp and dstemp ? the 28-pin devices have 3 i/o ports, while the 40/44-pin devices have 5 ? the 28-pin devices have 11 interrupts, while the 40/44-pin devices have 12 ? the 28-pin devices have 5 a/d input channels, while the 40/44-pin devices have 8 ? the parallel slave port is implemented only on the 40/44-pin devices the available features are summarized in table 1-1. block diagrams of the pic16cr73/76 and pic16cr74/77 devices are provided in figure 1-1 and figure 1-2, respectively. the pinouts for these device families are listed in table 1-2 and table 1-3. additional information may be found in the ? pic ? mid-range mcu family reference manual ? (ds33023), which may be obtained from your local microchip sales representative or downloaded from the microchip web site. the reference manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. table 1-1: pic16cr7x device features key features pic16cr73 pic16cr74 pic16cr76 pic16cr77 operating frequency dc ? 20 mhz dc ? 20 mhz dc ? 20 mhz dc ? 20 mhz resets (and delays) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) rom program memory (14-bit words) 4k 4k 8k 8k data memory (bytes) 192 192 368 368 interrupts 11 12 11 12 i/o ports ports a,b,c ports a,b,c,d,e ports a,b,c ports a,b,c,d,e timers 3333 capture/compare/pwm modules 2 2 2 2 serial communications ssp, usart ssp, usart ssp, usart ssp, usart parallel communications ? psp ? psp 8-bit analog-to-digital module 5 input channels 8 input channels 5 input channels 8 input channels instruction set 35 instructions 35 instructions 35 instructions 35 instructions packaging 28-pin dip 28-pin soic 28-pin ssop 28-pin mlf 40-pin pdip 44-pin plcc 44-pin tqfp 28-pin dip 28-pin soic 28-pin ssop 28-pin mlf 40-pin pdip 44-pin plcc 44-pin tqfp
pic16cr7x ds21993c-page 6 ? 2007 microchip technology inc. figure 1-1: pic16cr73 and pic16cr76 block diagram rom program memory 13 data bus 8 14 program bus instruction reg program counter 8-level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss rb0/int rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt 8 8 brown-out reset note 1: higher order bits are from the status register. usart ccp2 synchronous 8-bit a/d timer0 timer1 timer2 serial port ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 8 3 rb1 rb2 rb3 rb4 rb5 rb6 rb7 device program rom data memory pic16cr73 4k 192 bytes pic16cr76 8k 368 bytes ccp1
? 2007 microchip technology inc. ds21993c-page 7 pic16cr7x figure 1-2: pic16cr74 and pic16cr77 block diagram rom program memory 13 data bus 8 14 program bus instruction reg program counter 8-level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc portd porte ra4/t0cki ra5/an4/ss rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt re0/an5/rd re1/an6/wr re2/an7/cs 8 8 brown-out reset note 1: higher order bits are from the status register. usart ccp2 synchronous 8-bit a/d timer0 timer1 timer2 serial port ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 parallel slave port 8 3 rb0/int rb1 rb2 rb3 rb4 rb5 rb6 rb7 device program rom data memory pic16cr74 4k 192 bytes pic16cr77 8k 368 bytes rd0/psp0 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 ccp1
pic16cr7x ds21993c-page 8 ? 2007 microchip technology inc. table 1-2: pic16cr73 and pic16cr76 pinout description pin name pdip ssop soic pin# mlf pin# i/o/p type buffer type description osc1/clkin osc1 clkin 96 i i st/cmos (3) oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode. otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clkin, osc2/clkout pins). osc2/clkout osc2 clkout 10 7 o o ? oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonat or in crystal oscillator mode. in rc mode, osc2 pin outputs clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. mclr 1 26 i st master clear (reset) input. this pin is an active low reset to the device. porta is a bidirectional i/o port. ra0/an0 ra0 an0 227 i/o i ttl digital i/o. analog input 0. ra1/an1 ra1 an1 328 i/o i ttl digital i/o. analog input 1. ra2/an2 ra2 an2 41 i/o i ttl digital i/o. analog input 2. ra3/an3/v ref ra3 an3 v ref 52 i/o i i ttl digital i/o. analog input 3. a/d reference voltage input. ra4/t0cki ra4 t0cki 63 i/o i st digital i/o ? open drain when configured as output. timer0 external clock input. ra5/an4/ss ra5 an4 s s 74 i/o i i ttl digital i/o. analog input 4. spi slave select input. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int rb0 int 21 18 i/o i ttl/st (1) digital i/o. external interrupt. rb1 22 19 i/o ttl digital i/o. rb2 23 20 i/o ttl digital i/o. rb3 24 21 i/o ttl digital i/o. rb4 25 22 i/o ttl digital i/o. rb5 26 23 i/o ttl digital i/o. rb6 27 24 i/o ttl digital i/o. rb7 28 25 i/o ttl digital i/o. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial verify mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2007 microchip technology inc. ds21993c-page 9 pic16cr7x portc is a bidirectional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 11 8 i/o o i st digital i/o. timer1 oscillator output. timer1 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 12 9 i/o i i/o st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1 rc2 ccp1 13 10 i/o i/o st digital i/o. capture1 input/compare1 output/pwm1 output. rc3/sck/scl rc3 sck scl 14 11 i/o i/o i/o st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 15 12 i/o i i/o st digital i/o. spi data in. i 2 c? data i/o. rc5/sdo rc5 sdo 16 13 i/o o st digital i/o. spi data out. rc6/tx/ck rc6 tx ck 17 14 i/o o i/o st digital i/o. usart asynchronous transmit. usart 1 synchronous clock. rc7/rx/dt rc7 rx dt 18 15 i/o i i/o st digital i/o. usart asynchronous receive. usart synchronous data. v ss 8, 19 5, 16 p ? ground reference for logic and i/o pins. v dd 20 17 p ? positive supply for logic and i/o pins. table 1-2: pic16cr73 and pic16cr76 pinout description (continued) pin name pdip ssop soic pin# mlf pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial verify mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
pic16cr7x ds21993c-page 10 ? 2007 microchip technology inc. table 1-3: pic16cr74 and pic16cr77 pinout description pin name pdip pin# plcc pin# qfp pin# i/o/p type buffer type description osc1/clkin osc1 clkin 13 14 30 i i st/cmos (4) oscillator crystal or external clock input. oscillator crystal input or ex ternal clock source input. st buffer when configured in rc mode. otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clkin, osc2/clkout pins). osc2/clkout osc2 clkout 14 15 31 o o ? oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. mclr 1 2 18 i st master clear (reset) input. this pin is an active low reset to the device. porta is a bidirectional i/o port. ra0/an0 ra0 an0 2319 i/o i ttl digital i/o. analog input 0. ra1/an1 ra1 an1 3420 i/o i ttl digital i/o. analog input 1. ra2/an2 ra2 an2 4521 i/o i ttl digital i/o. analog input 2. ra3/an3/v ref ra3 an3 v ref 5622 i/o i i ttl digital i/o. analog input 3. a/d reference voltage input. ra4/t0cki ra4 t0cki 6723 i/o i st digital i/o ? open drain when configured as output. timer0 external clock input. ra5/an4/ss ra5 an4 s s 7824 i/o i i ttl digital i/o. analog input 4. spi slave select input. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial verify mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2007 microchip technology inc. ds21993c-page 11 pic16cr7x portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int rb0 int 33 36 8 i/o i ttl/st (1) digital i/o. external interrupt. rb1 34 37 9 i/o ttl digital i/o. rb2 353810 i/o ttl digital i/o. rb3 36 39 11 i/o ttl digital i/o. rb4 374114 i/o ttl digital i/o. rb5 384215 i/o ttl digital i/o. rb6 394316 i/o ttl digital i/o. rb7 404417 i/o ttl digital i/o. portc is a bidirectional i/o port. rc0/t1oso/ t1cki rc0 t1oso t1cki 15 16 32 i/o o i st digital i/o. timer1 oscillator output. timer1 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 16 18 35 i/o i i/o st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1 rc2 ccp1 17 19 36 i/o i/o st digital i/o. capture1 input/compare1 output/pwm1 output. rc3/sck/scl rc3 sck scl 18 20 37 i/o i/o i/o st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 23 25 42 i/o i i/o st digital i/o. spi data in. i 2 c? data i/o. rc5/sdo rc5 sdo 24 26 43 i/o o st digital i/o. spi data out. rc6/tx/ck rc6 tx ck 25 27 44 i/o o i/o st digital i/o. usart asynchronous transmit. usart 1 synchronous clock. rc7/rx/dt rc7 rx dt 26 29 1 i/o i i/o st digital i/o. usart asynchronous receive. usart synchronous data. table 1-3: pic16cr74 and pic16cr77 pinout description (continued) pin name pdip pin# plcc pin# qfp pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial verify mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
pic16cr7x ds21993c-page 12 ? 2007 microchip technology inc. portd is a bidirectional i/o port or parallel slave port when interfacing to a microprocessor bus. rd0/psp0 rd0 psp0 19 21 38 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 20 22 39 i i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 21 23 40 i i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 22 24 41 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd4/psp4 rd4 psp4 27 30 2 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd5/psp5 rd5 psp5 28 31 3 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd6/psp6 rd6 psp6 29 32 4 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd7/psp7 rd7 psp7 30 33 5 i/o i/o st/ttl (3) digital i/o. parallel slave port data. porte is a bidirectional i/o port. re0/an5/rd / re0 an5 rd 8925 i/o i i st/ttl (3) digital i/o. analog input 5. read control for parallel slave port . re1/an6/wr / re1 an6 wr 91026 i/o i i st/ttl (3) digital i/o. analog input 6. write control for parallel slave port . re2/an7/cs re2 an7 cs 10 11 27 i/o i i st/ttl (3) digital i/o. analog input 7. chip select control for parallel slave port . v ss 12,31 13,34 6,29 p ? ground reference for logic and i/o pins. v dd 11,32 12,35 7,28 p ? positive supply for logic and i/o pins. nc ? 1,17, 28, 40 12,13, 33, 34 ? these pins are not internally connected. these pins should be left unconnected. table 1-3: pic16cr74 and pic16cr77 pinout description (continued) pin name pdip pin# plcc pin# qfp pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial verify mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2007 microchip technology inc. ds21993c-page 13 pic16cr7x 2.0 memory organization there are two memory blocks in each of these pic ? mcus. the program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section. the program memory can be read internally by user code (see section 3.0 ?reading program memory? ). additional information on device memory may be found in the ? pic ? mid-range mcu family reference manual? (ds33023). 2.1 program memory organization the pic16cr7x devices have a 13-bit program counter capable of addressing an 8k word x 14-bit pro- gram memory space. the pic16cr77/76 devices have 8k words of rom program memory and the pic16cr73/74 devices have 4k words. the program memory maps for pic16cr7x devices are shown in figure 2-1. accessing a location above the physically implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. 2.2 data memory organization the data memory is partitioned into multiple banks, which contain the general purpose registers (gpr) and the special function registers (sfr). bits rp1 (status<6>) and rp0 (status<5>) are the bank select bits: each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some frequently used special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file (shown in figure 2-2 and figure 2-3) can be accessed either directly, or indirectly, through the file select register (fsr). figure 2-1: program memory maps and stacks for pic16cr7x devices rp1:rp0 bank 00 0 01 1 10 2 11 3 pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw 1fffh stack level 2 program memory page 0 page 1 07ffh 0800h 0fffh 1000h 17ffh 1800h reset vector interrupt vector page 0 page 1 page 2 page 3 0000h 0004h 0005h 1fffh 07ffh 0800h 0fffh 1000h pc<12:0> 13 stack level 1 stack level 8 call, return retfie, retlw stack level 2 unimplemented read as ? 0 ? on-chip program memory pic16cr76/77 pic16cr73/74
pic16cr7x ds21993c-page 14 ? 2007 microchip technology inc. figure 2-2: pic16cr77/76 register file map indirect addr.(*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations, read as ? 0 ?. * not a physical register. note 1: these registers are not implemented on 28-pin devices. file address indirect addr.(*) indirect addr.(*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 10ch 10dh 10eh 10fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11ah 11bh 11ch 11dh 11eh 11fh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 18ch 18dh 18eh 18fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19ah 19bh 19ch 19dh 19eh 19fh 120h 1a0h 17fh 1ffh bank 2 bank 3 indirect addr.(*) portd (1) porte (1) trisd (1) trise (1) tmr0 option_reg pir2 pie2 rcsta txreg rcreg ccpr2l ccpr2h ccp2con adres adcon0 txsta spbrg adcon1 general purpose register general purpose register general purpose register general purpose register 1efh 1f0h accesses 70h-7fh efh f0h accesses 70h-7fh 16fh 170h accesses 70h-7fh general purpose register general purpose register trisb portb 96 bytes 80 bytes 80 bytes 80 bytes 16 bytes 16 bytes pmdata pmadr pmcon1 pmdath pmadrh file address file address file address sspadd
? 2007 microchip technology inc. ds21993c-page 15 pic16cr7x figure 2-3: pic16cr74/73 register file map indirect addr.(*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 file address indirect addr.(*) indirect addr.(*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 17fh 1ffh bank 2 bank 3 indirect addr.(*) portd (1) porte (1) trisd (1) trise (1) tmr0 option_reg pir2 pie2 rcsta txreg rcreg ccpr2l ccpr2h ccp2con adres adcon0 txsta spbrg adcon1 general purpose register general purpose register 1efh 1f0h accesses a0h-ffh 16fh 170h accesses 20h-7fh trisb portb 96 bytes 96 bytes 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h pmdata pmadr pmcon1 pmdath pmadrh unimplemented data memory locations, read as ? 0 ?. * not a physical register. note 1: these registers are not implemented on 28-pin devices. 120h 1a0h file address file address file address sspadd
pic16cr7x ds21993c-page 16 ? 2007 microchip technology inc. 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. the special function registers can be classified into two sets: core (cpu) and peripheral. those registers associated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in the peripheral feature section. table 2-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page bank 0 00h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 27, 96 01h tmr0 timer0 module register xxxx xxxx 45, 96 02h (4) pcl program counter (pc) least significant byte 0000 0000 26, 96 03h (4) status irp rp1 rp0 to pd zdc c (2) 0001 1xxx 19, 96 04h (4) fsr indirect data memory address pointer xxxx xxxx 27, 96 05h porta ? ? porta data latch when written: porta pins when read --0x 0000 32, 96 06h portb portb data latch when written: portb pins when read xxxx xxxx 34, 96 07h portc portc data latch when written: portc pins when read xxxx xxxx 35, 96 08h (5) portd portd data latch when written: portd pins when read xxxx xxxx 36, 96 09h (5) porte ? ? ? ? ? re2 re1 re0 ---- -xxx 39, 96 0ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 26, 96 0bh (4) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 21, 96 0ch pir1 pspif (3) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 23, 96 0dh pir2 ? ? ? ? ? ? ?ccp2if ---- ---0 24, 96 0eh tmr1l holding register for the least signif icant byte of the 16-bit tmr1 register xxxx xxxx 50, 96 0fh tmr1h holding register for the most signi ficant byte of the 16-bit tmr1 register xxxx xxxx 50, 96 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 47, 96 11h tmr2 timer2 module register 0000 0000 52, 96 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 52, 96 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx 64, 68, 96 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 61, 96 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx 56, 96 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx 56, 96 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 54, 96 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 70, 96 19h txreg usart transmit data register 0000 0000 75, 96 1ah rcreg usart receive data register 0000 0000 77, 96 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx 58, 96 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx 58, 96 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 54, 96 1eh adres a/d result register byte xxxx xxxx 88, 96 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/ done ?adon 0000 00-0 83, 96 legend: x = unknown, u = unchanged, q = value depends on condition, ? = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program c ounter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter during branches ( call or goto ). 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd and trise are not physically implemented on the 28-pin devices, read as ? 0 ?. 6: this bit always reads as a ? 1 ?.
? 2007 microchip technology inc. ds21993c-page 17 pic16cr7x bank 1 80h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 27, 96 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 20, 44, 96 82h (4) pcl program counter (pc) least significant byte 0000 0000 26, 96 83h (4) status irp rp1 rp0 to pd zdc c (2) 0001 1xxx 19, 96 84h (4) fsr indirect data memory address pointer xxxx xxxx 27, 96 85h trisa ? ? porta data direction register --11 1111 32, 96 86h trisb portb data direction register 1111 1111 34, 96 87h trisc portc data direction register 1111 1111 35, 96 88h (5) trisd portd data direction register 1111 1111 36, 96 89h (5) trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 38, 96 8ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 26, 96 8bh (4) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 21, 96 8ch pie1 pspie (3) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 22, 97 8dh pie2 ? ? ? ? ? ? ?ccp2ie ---- ---0 24, 97 8eh pcon ? ? ? ? ? ?por bor ---- --qq 22, 97 8fh ? unimplemented ? ? 90h ? unimplemented ? ? 91h ? unimplemented ? ? 92h pr2 timer2 module period register 1111 1111 52, 97 93h sspadd synchronous serial port (i 2 c? mode) address register 0000 0000 68, 97 94h sspstat smp cke d/a psr/w ua bf 0000 0000 60, 97 95h ? unimplemented ? ? 96h ? unimplemented ? ? 97h ? unimplemented ? ? 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 69, 97 99h spbrg baud rate generator register 0000 0000 71, 97 9ah ? unimplemented ? 9bh ? unimplemented ? 9ch ? unimplemented ? 9dh ? unimplemented ? 9eh ? unimplemented ? 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 84, 97 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page legend: x = unknown, u = unchanged, q = value depends on condition, ? = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program c ounter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program count er during branches ( call or goto ). 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd and trise are not physically implemented on the 28-pin devices, read as ? 0 ?. 6: this bit always reads as a ? 1 ?.
pic16cr7x ds21993c-page 18 ? 2007 microchip technology inc. bank 2 100h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 27, 96 101h tmr0 timer0 module register xxxx xxxx 45, 96 102h (4) pcl program counter (pc) least significant byte 0000 0000 26, 96 103h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 19, 96 104h (4) fsr indirect data memory address pointer xxxx xxxx 27, 96 105h ? unimplemented ? ? 106h portb portb data latch when written: portb pins when read xxxx xxxx 34, 96 107h ? unimplemented ? ? 108h ? unimplemented ? ? 109h ? unimplemented ? ? 10ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 26, 96 10bh (4) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 21, 96 10ch pmdata data register low byte xxxx xxxx 29, 97 10dh pmadr address register low byte xxxx xxxx 29, 97 10eh pmdath ? ? data register high byte xxxx xxxx 29, 97 10fh pmadrh ? ? ? address register high byte xxxx xxxx 29, 97 bank 3 180h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 27, 96 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 20, 44, 96 182h (4) pcl program counter (pc) least significant byte 0000 0000 26, 96 183h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 19, 96 184h (4) fsr indirect data memory address pointer xxxx xxxx 27, 96 185h ? unimplemented ? ? 186h trisb portb data direction register 1111 1111 34, 96 187h ? unimplemented ? ? 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 26, 96 18bh (4) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 21, 96 18ch pmcon1 ? (6) ? ? ? ? ? ?rd 1--- ---0 29, 97 18dh ? unimplemented ? 18eh ? reserved maintain clear 0000 0000 18fh ? reserved maintain clear 0000 0000 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page legend: x = unknown, u = unchanged, q = value depends on condition, ? = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program c ounter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter during branches ( call or goto ). 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd and trise are not physically implemented on the 28-pin devices, read as ? 0 ?. 6: this bit always reads as a ? 1 ?.
? 2007 microchip technology inc. ds21993c-page 19 pic16cr7x 2.2.2.1 status register the status register contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable, therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ?000u u1uu? (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect the z, c or dc bits from the status register. for other instructions not affecting any status bits, see the ?instruction set summary.? note 1: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. register 2-1: status: (address 03h, 83h, 103h, 183h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h-1ffh) 0 = bank 0, 1 (00h-ffh) bit 6-5 rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h-1ffh) 10 = bank 2 (100h-17fh) 01 = bank 1 (80h-ffh) 00 = bank 0 (00h-7fh) each bank is 128 bytes bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit ( addwf , addlw, sublw, subwf instructions) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c: carry/borrow bit ( addwf, addlw, sublw, subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16cr7x ds21993c-page 20 ? 2007 microchip technology inc. 2.2.2.2 option_reg register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0 and the weak pull-ups on portb. note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. register 2-2: option_reg: (address 81h, 181h) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
? 2007 microchip technology inc. ds21993c-page 21 pic16cr7x 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. register 2-3: intcon: (address 0bh, 8bh, 10bh, 18bh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie tmr0ie inte rbie tmr0if intf rbif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie : peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif : rb port change interrupt flag bit a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state
pic16cr7x ds21993c-page 22 ? 2007 microchip technology inc. 2.2.2.4 pie1 register the pie1 register contains the individual enable bits for the peripheral interrupts. note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. register 2-4: pie1: (address 8ch) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5 rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2 ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt note 1: pspie is reserved on 28-pin devices; always maintain this bit clear.
? 2007 microchip technology inc. ds21993c-page 23 pic16cr7x 2.2.2.5 pir1 register the pir1 register contains the individual flag bits for the peripheral interrupts. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. register 2-5: pir1: (address 0ch) r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion is completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty 0 = the usart transmit buffer is full bit 3 sspif : synchronous serial port (ssp) interrupt flag 1 = the ssp interrupt condition has occurred, and must be cleared in software before returning from the interrupt service routin e. the conditions that will set this bit are: spi a transmission/reception has taken place. i 2 c slave a transmission/reception has taken place. i 2 c master a transmission/reception has taken place. the initiated start condition was completed by the ssp module. the initiated stop condition was completed by the ssp module. the initiated restart condition was completed by the ssp module. the initiated acknowledge condition was completed by the ssp module. a start condition occurred while the ssp module was idle (multi-master system). a stop condition occurred while the ssp module was idle (multi-master system). 0 = no ssp interrupt condition has occurred bit 2 ccp1if : ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode bit 1 tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow note 1: pspif is reserved on 28-pin devices; always maintain this bit clear.
pic16cr7x ds21993c-page 24 ? 2007 microchip technology inc. 2.2.2.6 pie2 register the pie2 register contains the individual enable bits for the ccp2 peripheral interrupt. 2.2.2.7 pir2 register the pir2 register contains the flag bits for the ccp2 interrupt. register 2-6: pie2: (address 8dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? ccp2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 unimplemented: read as ? 0 ? bit 0 ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. register 2-7: pir2: (address 0dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ccp2if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 unimplemented: read as ? 0 ? bit 0 ccp2if : ccp2 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused
? 2007 microchip technology inc. ds21993c-page 25 pic16cr7x 2.2.2.8 pcon register the power control (pcon) register contains flag bits to allow differentiation between a power-on reset (por), a brown-out reset (bor), a watchdog reset (wdt) and an external mclr reset. note: bor is unknown on por. it must be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is not predictable if the brown-out circuit is disabled (by clearing the boren bit in the configuration word). register 2-8: pcon: (address 8eh) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-1 ? ? ? ? ? ? por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 unimplemented: read as ? 0 ? bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
pic16cr7x ds21993c-page 26 ? 2007 microchip technology inc. 2.3 pcl and pclath the program counter (pc) is 13 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the upper bits (pc<12:8>) are not readable, but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 2-1 shows the two situations for the loading of the pc. the upper example in the figure shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in the figure shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 2-4: loading of pc in different situations 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note, ?implementing a table read? (an556). 2.3.2 stack the pic16cr7x family has an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed, or an inter- rupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execu- tion. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging pic16cr7x devices are capable of addressing a con- tinuous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is exe- cuted, the entire 13-bit pc is popped off the stack. therefore, manipulation of the pclath<4:3> bits are not required for the return instructions (which pops the address from the stack). example 2-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt service routine (if interrupts are used). example 2-1: call of a subroutine in page 1 from page 0 pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions, or the vectoring to an interrupt address. note: the contents of the pclath are unchanged after a return or retfie instruction is executed. the user must setup the pclath for any subsequent calls or gotos . org 0x500 bcf pclath,4 bsf pclath,3 ;select page 1 ;(800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : org 0x900 ;page 1 (800h-fffh) sub1_p1 : ;called subroutine : ;page 1 (800h-fffh) : return ;return to call ;subroutine in page 0 ;(000h-7ffh)
? 2007 microchip technology inc. ds21993c-page 27 pic16cr7x 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister (fsr). reading the indf register itself indirectly (fsr = 0 ) will read 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-2. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-2. example 2-2: indirect addressing figure 2-5: direct/indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue note 1: for register file map detail, see figure 2-2. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h
pic16cr7x ds21993c-page 28 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21993c-page 29 pic16cr7x 3.0 reading pr ogram memory the rom program memory is readable during normal operation over the entire v dd range. it is indirectly addressed through special function registers (sfr). up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ascii, etc. executing a program memory location containing data that forms an invalid instruction results in a nop . there are five sfrs used to read the program and memory. these registers are: ?pmcon1 ?pmdata ?pmdath ?pmadr ? pmadrh the program memory allows word reads. program memory access allows for checksum calculation and reading calibration tables. when interfacing to the program memory block, the pmdath:pmdata registers form a two-byte word, which holds the 14-bit data for reads. the pmadrh:pmadr registers form a two-byte word, which holds the 13-bit address of the rom location being accessed. these devices can have up to 8k words of program rom, with an address range from 0h to 3fffh. the unused upper bits in both the pmdath and pmadrh registers are not implemented and read as ? 0 ?s. 3.1 pmadr the address registers can address up to a maximum of 8k words of program rom. when selecting a program address value, the msb of the address is written to the pmadrh register and the lsb is written to the pmadr register. the upper msb?s of pmadrh must always be clear. 3.2 pmcon1 register pmcon1 is the control register for memory accesses. the control bit rd initiates read operations. this bit cannot be cleared, only set, in software. it is cleared in hardware at the completion of the read operation. register 3-1: pmcon1: (address 18ch) r-1 u-0 u-0 u-0 u-x u-0 u-0 r/s-0 reserved ? ? ? ? ? ?rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 reserved: read as ? 1 ? bit 6-1 unimplemented : read as ? 0 ? bit 0 rd : read control bit 1 = initiates a rom read, rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = rom read completed
pic16cr7x ds21993c-page 30 ? 2007 microchip technology inc. 3.3 reading the rom program memory a program memory location may be read by writing two bytes of the address to the pmadr and pmadrh reg- isters and then setting control bit rd (pmcon1<0>). once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data. the data is available in the pmdata and pmdath regis- ters after the second nop instruction. therefore, it can be read as two bytes in the following instructions. the pmdata and pmdath registers will hold this value until the next read operation. 3.4 operation during code-protect rom program memory has its own code-protect mech- anism. external read operations by programmers are disabled if this mechanism is enabled. the microcontroller can read and execute instructions out of the internal rom program memory, regardless of the state of the code-protect configuration bits. example 3-1: rom program read table 3-1: registers associated with program rom address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 10dh pmadr address register low byte xxxx xxxx uuuu uuuu 10fh pmadrh ? ? ? address register high byte xxxx xxxx uuuu uuuu 10ch pmdata data register low byte xxxx xxxx uuuu uuuu 10eh pmdath ? ? data register high byte xxxx xxxx uuuu uuuu 18ch pmcon1 ? (1) ? ? ? ? ? ? rd 1--- ---0 1--- ---0 legend: x = unknown, u = unchanged, r = reserved, ? = unimplemented read as ? 0 ?. shaded cells are not used during rom access. note 1: this bit always reads as a ? 1 ?. bsf status, rp1 ; bcf status, rp0 ; bank 2 movf addrh, w ; movwf pmadrh ; msbyte of program address to read movf addrl, w ; movwf pmadr ; lsbyte of program address to read bsf status, rp0 ; bank 3 required required bsf pmcon1, rd ; rom read sequence sequence nop ; memory is read in the next two cycles after bsf pmcon1,rd nop ; bcf status, rp0 ; bank 2 movf pmdata, w ; w = lsbyte of program pmdata movf pmdath, w ; w = msbyte of program pmdata
? 2007 microchip technology inc. ds21993c-page 31 pic16cr7x 4.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the ? pic ? mid-range mcu family reference manual ? (ds33023). 4.1 porta and the trisa register porta is a 6-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impendance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other porta pins have ttl input levels and full cmos output drivers. other porta pins are multiplexed with analog inputs and analog v ref input. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set, when using them as analog inputs. example 4-1: initializing porta figure 4-1: block diagram of ra3:ra0 and ra5 pins figure 4-2: block diagram of ra4/t0cki pin note: on a power-on reset, these pins are configured as analog inputs and read as ? 0 ?. bcf status, rp0 ; bcf status, rp1 ; bank0 clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x06 ; configure all pins movwf adcon1 ; as digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6>are always ; read as ?0?. data bus p n wr port wr tris rd tris rd port v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter en qd en data latch tris latch q d q ck q d q ck data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en note 1: i/o pin has protection diodes to v ss only.
pic16cr7x ds21993c-page 32 ? 2007 microchip technology inc. table 4-1: porta functions table 4-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit 0 ttl input/output or analog input. ra1/an1 bit 1 ttl input/output or analog input. ra2/an2 bit 2 ttl input/output or analog input. ra3/an3/v ref bit 3 ttl input/output or analog input or v ref. ra4/t0cki bit 4 st input/output or external clock input for timer0. output is open drain type. ra5/an4/ss bit 5 ttl input/output or slave select input for synchronous serial port or analog input. legend: ttl = ttl input, st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note: when using the ssp module in spi slave mode and ss enabled, the a/d converter must be set to one of the following modes where pcfg2:pcfg0 = 100, 101, 11x .
? 2007 microchip technology inc. ds21993c-page 33 pic16cr7x 4.2 portb and the trisb register portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impendance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. figure 4-3: block diagram of rb3:rb0 pins four of the portb pins (rb7:rb4) have an interrupt- on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. this interrupt on mismatch feature, together with soft- ware configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. refer to the embedded control handbook, ? implementing wake-up on key stroke ? (an552). rb0/int is an external interrupt input pin and is configured using the intedg bit (option_reg<6>). rb0/int is discussed in detail in section 12.11.1 ?int interrupt? . figure 4-4: block diagram of rb7:rb4 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) q3 q1 note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>).
pic16cr7x ds21993c-page 34 ? 2007 microchip technology inc. table 4-3: portb functions table 4-4: summary of registers associated with portb name bit# buffer function rb0/int bit 0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit 1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit 2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit 3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit 4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5 bit 5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb6 bit 6 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb7 bit 7 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
? 2007 microchip technology inc. ds21993c-page 35 pic16cr7x 4.3 portc and the trisc register portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impendance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). portc is multiplexed with several peripheral functions (table 4-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings, and to section 13.1 ?read-mod- ify-write operations? for additional information on read-modify-write operations. figure 4-5: portc block diagram (peripheral output override) table 4-5: portc functions table 4-6: summary of registers associated with portc port/peripheral select (2) data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss peripheral oe (3) peripheral input note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. i/o pin (1) name bit# buffer type function rc0/t1oso/t1cki bit 0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi/ccp2 bit 1 st input/output port pin or timer1 oscillator input or capture2 input/ compare2 output/pwm2 output. rc2/ccp1 bit 2 st input/output port pin or capture1 input/compare1 output/pwm1 output. rc3/sck/scl bit 3 st rc3 can also be the synchronous serial clock for both spi and i 2 c? modes. rc4/sdi/sda bit 4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c? mode). rc5/sdo bit 5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit 6 st input/output port pin or usart asynchronous transmit or synchronous clock. rc7/rx/dt bit 7 st input/output port pin or usart asynchronous receive or synchronous data. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
pic16cr7x ds21993c-page 36 ? 2007 microchip technology inc. 4.4 portd and trisd registers this section is not applicable to the pic16cr73 or pic16cr76. portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configureable as an input or output. portd can be configured as an 8-bit wide micro- processor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. figure 4-6: portd block diagram (in i/o port mode) table 4-7: portd functions table 4-8: summary of registers associated with portd data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en name bit# buffer type function rd0/psp0 bit 0 st/ttl (1) input/output port pin or parallel slave port bit 0 rd1/psp1 bit 1 st/ttl (1) input/output port pin or parallel slave port bit 1 rd2/psp2 bit 2 st/ttl (1) input/output port pin or parallel slave port bit 2 rd3/psp3 bit 3 st/ttl (1) input/output port pin or parallel slave port bit 3 rd4/psp4 bit 4 st/ttl (1) input/output port pin or parallel slave port bit 4 rd5/psp5 bit 5 st/ttl (1) input/output port pin or parallel slave port bit 5 rd6/psp6 bit 6 st/ttl (1) input/output port pin or parallel slave port bit 6 rd7/psp7 bit 7 st/ttl (1) input/output port pin or parallel slave port bit legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?. shaded cells are not used by portd.
? 2007 microchip technology inc. ds21993c-page 37 pic16cr7x 4.5 porte and trise register this section is not applicable to the pic16cr73 or pic16cr76. porte has three pins, re0/rd /an5, re1/wr /an6 and re2/cs /an7, which are individually configureable as inputs or outputs. these pins have schmitt trigger input buffers. i/o porte becomes control inputs for the micro- processor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs). ensure adcon1 is configured for digital i/o. in this mode, the input buffers are ttl. register 4-1 shows the trise register, which also controls the parallel slave port operation. porte pins are multiplexed with analog inputs. when selected as an analog input, these pins will read as ? 0 ?s. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. figure 4-7: port e block diagram (in i/o port mode) note: on a power-on reset, these pins are configured as analog inputs and read as ? 0 ?. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en
pic16cr7x ds21993c-page 38 ? 2007 microchip technology inc. register 4-1: trise: (address 89h) r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? bit 2 bit 1 bit 0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 parallel slave port status/control bits: ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3 unimplemented : read as ? 0 ? bit 2 porte data direction bits: bit 2 : direction control bit for pin re2/cs /an7 1 = input 0 = output bit 1 bit 1 : direction control bit for pin re1/wr /an6 1 = input 0 = output bit 0 bit 0 : direction control bit for pin re0/rd /an5 1 = input 0 = output
? 2007 microchip technology inc. ds21993c-page 39 pic16cr7x table 4-9: porte functions table 4-10: summary of registers associated with porte name bit# buffer type function re0/rd /an5 bit 0 st/ttl (1) input/output port pin or read control input in parallel slave port mode or analog input. for rd (psp mode): 1 = idle 0 = read operation. contents of portd register output to portd i/o pins (if chip selected). re1/wr /an6 bit 1 st/ttl (1) input/output port pin or write control input in parallel slave port mode or analog input. for wr (psp mode): 1 =idle 0 = write operation. value of portd i/o pins latched into portd register (if chip selected). re2/cs /an7 bit 2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode or analog input. for cs (psp mode): 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 09h porte ? ? ? ? ?re2re1re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by porte.
pic16cr7x ds21993c-page 40 ? 2007 microchip technology inc. 4.6 parallel slave port the parallel slave port (psp) is not implemented on the pic16cr73 or pic16cr76. portd operates as an 8-bit wide parallel slave port, or microprocessor port, when control bit pspmode (trise<4>) is set. in slave mode, it is asynchronously readable and writable by an external system using the read control input pin re0/rd , the write control input pin re1/wr , and the chip select control input pin re2/ cs . the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (i.e., set). the a/d port configuration bits pcfg3:pcfg0 (adcon1<3:0>) must be set to configure pins re2:re0 as digital i/o. there are actually two 8-bit latches, one for data output (external reads) and one for data input (external writes). the firmware writes 8-bit data to the portd output data latch and reads data from the portd input data latch (note that they have the same address). in this mode, the trisd register is ignored, since the external device is controlling the direction of data flow. an external write to the psp occurs when the cs and wr lines are both detected low. firmware can read the actual data on the portd pins during this time. when either the cs or wr lines become high (level trig- gered), the data on the portd pins is latched, and the input buffer full (ibf) status flag bit (trise<7>) and interrupt flag bit pspif (pir1<7>) are set on the q4 clock cycle, following the next q2 cycle to signal the write is complete (figure 4-9). firmware clears the ibf flag by reading the latched portd data and clears the pspif bit. the input buffer overflow (ibov) status flag bit (trise<5>) is set if an external write to the psp occurs while the ibf flag is set from a previous external write. the previous portd data is overwritten with the new data. ibov is cleared by reading portd and clearing ibov. a read from the psp occurs when both the cs and rd lines are detected low. the data in the portd output latch is output to the portd pins. the output buffer full (obf) status flag bit (trise<6>) is cleared imme- diately (figure 4-10), indicating that the portd latch is being read, or has been read by the external bus. if firmware writes new data to the output latch during this time, it is immediately output to the portd pins, but obf will remain cleared. when either the cs or rd pins are detected high, the portd outputs are disabled, and the interrupt flag bit pspif is set on the q4 clock cycle following the next q2 cycle, indicating that the read is complete. obf remains low until firmware writes new data to portd. when not in psp mode, the ibf and obf bits are held clear. flag bit ibov remains unchanged. the pspif bit must be cleared by the user in firmware; the interrupt can be disabled by clearing the interrupt enable bit pspie (pie1<7>). figure 4-8: portd and porte block diagram (parallel slave port) data bus wr port rd rdx q d ck en qd en port pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl
? 2007 microchip technology inc. ds21993c-page 41 pic16cr7x figure 4-9: parallel slave port write waveforms figure 4-10: parallel slave port read waveforms table 4-11: registers associated with parallel slave port address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 08h portd port data latch when written: port pins when read xxxx xxxx uuuu uuuu 09h porte ? ? ? ? ?re2re1re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port. note 1: bits pspie and pspif are reserved on the pic16cr73/76; always maintain these bits clear. q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0>
pic16cr7x ds21993c-page 42 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21993c-page 43 pic16cr7x 5.0 timer0 module the timer0 module timer/counter has the following features: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock additional information on the timer0 module is available in the ? pic ? mid-range mcu family reference manual ? (ds33023). figure 5-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. timer0 operation is controlled through the option_reg register (register 5-1 on the following page). timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment, either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed in detail in section 5.2 ?using timer0 with an external clock? . the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the prescaler is not readable or writable. section 5.3 ?prescaler? details the operation of the prescaler. 5.1 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit tmr0if (intcon<2>). the interrupt can be masked by clearing bit tmr0ie (intcon<5>). bit tmr0if must be cleared in software by the timer0 module interrupt service routine, before re-enabling this inter- rupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut-off during sleep. figure 5-1: block diagram of the timer0 module and prescaler ra4/t0cki t0se pin m u x clkout (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1 mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit tmr0if on overflow 8 psa t0cs prescaler
pic16cr7x ds21993c-page 44 ? 2007 microchip technology inc. 5.2 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki, with the internal phase clocks, is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. register 5-1: option_reg: r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbpu : portb pull-up enable bit (see section 2.2.2.2 ?option_reg register? ) bit 6 intedg : interrupt edge select bit (see section 2.2.2.2 ?option_reg register? ) bit 5 t0cs: tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate note: to avoid an unintended device reset, the instruction sequences shown in example 5-1 and example 5-2 must be executed when changing the prescaler assignment between timer0 and the wdt. this sequence must be followed even if the wdt is disabled.
? 2007 microchip technology inc. ds21993c-page 45 pic16cr7x 5.3 prescaler there is only one prescaler available on the microcon- troller; it is shared exclusively between the timer0 mod- ule and the watchdog timer. the usage of the prescaler is also mutually exclusive: that is, a prescaler assign- ment for the timer0 module means that there is no pres- caler for the watchdog timer, and vice versa. this prescaler is not readable or writable (see figure 5-1). the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. examples of code for assigning the prescaler assign- ment are shown in example 5-1 and example 5-2. note that when the prescaler is being assigned to the wdt with ratios other than 1:1, lines 2 and 3 (high- lighted) are optional. if a prescale ratio of 1:1 is used, however, these lines must be used to set a temporary value. the final 1:1 value is then set in lines 10 and 11 (highlighted). (line numbers are included in the example for illustrative purposes only, and are not part of the actual code.) when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. example 5-1: changing the prescaler assignment from timer0 to wdt example 5-2: changing the prescaler assignment from wdt to timer0 table 5-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 01h,101h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by timer0. 1) bsf status, rp0 ; bank1 2) movlw b?xx0x0xxx? ; select clock source and prescale value of 3) movwf option_reg ; other than 1:1 4) bcf status, rp0 ; bank0 5) clrf tmr0 ; clear tmr0 and prescaler 6) bsf status, rp1 ; bank1 7) movlw b?xxxx1xxx? ; select wdt, do not change prescale value 8) movwf option_reg 9) clrwdt ; clears wdt and prescaler 10) movlw b?xxxx1xxx? ; select new prescale value and wdt 11) movwf option_reg 12) bcf status, rp0 ; bank0 clrwdt ; clear wdt and prescaler bsf status, rp0 ; bank1 movlw b?xxxx0xxx? ; select tmr0, new prescale movwf option_reg ; value and clock source bcf status, rp0 ; bank0
pic16cr7x ds21993c-page 46 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21993c-page 47 pic16cr7x 6.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l), which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit tmr1ie (pie1<0>). timer1 can operate in one of two modes: ?as a timer ?as a counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). timer1 also has an internal ?reset input?. this reset can be generated by either of the two ccp modules as the special event trigger (see sections 8.1 and 8.2). register 6-1 shows the timer1 control register. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi/ccp2 and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored and these pins read as ? 0 ?. additional information on timer modules is available in the ? pic ? mid-range mcu family reference manual ? (ds33023). register 6-1: t1con: timer1 control (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1
pic16cr7x ds21993c-page 48 ? 2007 microchip technology inc. 6.1 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit t1sync (t1con<2>) has no effect, since the internal clock is always in sync. 6.2 timer1 counter operation timer1 may operate in asynchronous or synchronous mode, depending on the setting of the tmr1cs bit. when timer1 is being incremented via an external source, increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. figure 6-1: timer1 incrementing edge 6.3 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rc1/t1osi/ccp2, when bit t1oscen is set, or on pin rc0/t1oso/t1cki, when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the prescaler stage is an asynchronous ripple counter. in this configuration, during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. the prescaler, however, will continue to increment. figure 6-2: timer1 block diagram t1cki (default high) t1cki (default low) note: arrows indicate counter increments. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 q clock t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi/ccp2 (2) note 1: when the t1oscen bit is cleared, the inverter is turned off. this eliminates power drain. 2: for the pic16cr73/76, the schmitt trigger is not implemented in external clock mode. set flag bit tmr1if on overflow tmr1 (2)
? 2007 microchip technology inc. ds21993c-page 49 pic16cr7x 6.4 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in soft- ware are needed to read/write the timer ( section 6.4.1 ?reading and writing timer1 in asynchronous counter mode? ). in asynchronous counter mode, timer1 cannot be used as a time base for capture or compare operations. 6.4.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. the example code provided in example 6-1 and example 6-2 demonstrates how to write to and read timer1 while it is running in asynchronous mode. example 6-1: writing a 16-bit free-running timer example 6-2: reading a 16-bit free-running timer ; all interrupts are disabled clrf tmr1l ; clear low byte, ensures no rollover into tmr1h movlw hi_byte ; value to load into tmr1h movwf tmr1h, f ; write high byte movlw lo_byte ; value to load into tmr1l movwf tmr1h, f ; write low byte ; re-enable the interrupt (if required) continue ; continue with your code ; all interrupts are disabled movf tmr1h, w ; read high byte movwf tmph movf tmr1l, w ; read low byte movwf tmpl movf tmr1h, w ; read high byte subwf tmph, w ; sub 1st read with 2nd read btfsc status,z ; is result = 0 goto continue ; good 16-bit read ; tmr1l may have rolled over between the read of the high and low bytes. ; reading the high and low bytes now will read a good value. movf tmr1h, w ; read high byte movwf tmph movf tmr1l, w ; read low byte movwf tmpl ; re-enable the interrupt (if required) continue ; continue with your code
pic16cr7x ds21993c-page 50 ? 2007 microchip technology inc. 6.5 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low-power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for use with a 32 khz crystal. table 6-1 shows the capaci- tor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. 6.6 resetting timer1 using a ccp trigger output if the ccp1 or ccp2 module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1. timer1 must be configured for either timer or synchro- nized counter mode, to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1 or ccp2, the write will take precedence. in this mode of operation, the ccprxh:ccprxl regis- ter pair effectively becomes the period register for timer1. 6.7 resetting of timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por, or any other reset, except by the ccp1 and ccp2 special event triggers. table 6-1: capacitor selection for the timer1 oscillator t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 6.8 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. table 6-2: registers associated with timer1 as a timer/counter note: the special event triggers from the ccp1 and ccp2 modules will not set interrupt flag bit tmr1if (pir1<0>). osc type frequency capacitors used: osc1 osc2 lp 32 khz 47 pf 47 pf 100 khz 33 pf 33 pf 200 khz 15 pf 15 pf capacitor values are for design guidance only. these capacitors were tested with the crystals listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes (below) table for additional information. commonly used crystals: 32.768 khz epson c-001r32.768k-a 100 khz epson c-2 100.00 kc-p 200 khz std xtl 200.000 khz note 1: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. note 1: bits pspie and pspif are reserved on the pic16cr73/76; always maintain these bits clear.
? 2007 microchip technology inc. ds21993c-page 51 pic16cr7x 7.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time base for the pwm mode of the ccp module(s). the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). timer2 can be shut-off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. register 7-1 shows the timer2 control register. additional information on timer modules is available in the ? pic ? mid-range mcu family reference manual ? (ds33023). 7.1 timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (por, mclr reset, wdt reset or bor) tmr2 is not cleared when t2con is written. 7.2 output of tmr2 the output of tmr2 (before the postscaler) is fed to the ssp module, which optionally uses it to generate shift clock. figure 7-1: timer2 block diagram comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. 1:1 to 1:16 t2outps3: t2outps0 t2ckps1: t2ckps0
pic16cr7x ds21993c-page 52 ? 2007 microchip technology inc. table 7-1: registers associated with timer2 as a timer/counter register 7-1: t2con: timer2 control (address 12h) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 module register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. note 1: bits pspie and pspif are reserved on the pic16cr73/76; always maintain these bits clear.
? 2007 microchip technology inc. ds21993c-page 53 pic16cr7x 8.0 capture/compare/pwm modules each capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: ? 16-bit capture register ? 16-bit compare register ? pwm master/slave duty cycle register both the ccp1 and ccp2 modules are identical in operation, with the exception being the operation of the special event trigger. table 8-1 and table 8-2 show the resources and interactions of the ccp module(s). in the following sections, the operation of a ccp module is described with respect to ccp1. ccp2 operates the same as ccp1, except where noted. 8.1 ccp1 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. the special event trigger is generated by a compare match and will clear both tmr1h and tmr1l registers. 8.2 ccp2 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp2con register controls the operation of ccp2. the special event trigger is generated by a compare match; it will clear both tmr1h and tmr1l registers, and start an a/d conver- sion (if the a/d module is enabled). additional information on ccp modules is available in the ? pic ? mid-range mcu family reference manual ? (ds33023) and in application note an594, ? using the ccp modules ? (ds00594). table 8-1: ccp mode ? timer resources required table 8-2: interaction of two ccp modules ccp mode timer resource capture timer1 compare timer1 pwm timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time base. capture compare same tmr1 time base. compare compare same tmr1 time base. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). the rising edges are aligned. pwm capture none. pwm compare none.
pic16cr7x ds21993c-page 54 ? 2007 microchip technology inc. register 8-1: ccp1con/ccp2con: (address 17h/1dh) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 ccpxx:ccpxy : pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set, ccpx pin is unaffected); ccp1 clears timer1; ccp2 clears timer1 and starts an a/d conversion (if a/d module is enabled) 11xx =pwm mode
? 2007 microchip technology inc. ds21993c-page 55 pic16cr7x 8.3 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as one of the following and is configured by ccpxcon<3:0>: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new captured value. 8.3.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be configured as an input by setting the trisc<2> bit. figure 8-1: capture mode operation block diagram 8.3.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 8.3.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if following any such change in operating mode. 8.3.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 8-1 shows the recom- mended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 8-1: changing between capture prescalers 8.4 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: ? driven high ?driven low ? remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 8-2: compare mode operation block diagram note: if the rc2/ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable q?s ccp1con<3:0> rc2/ccp1 prescaler 1, 4, 16 and edge detect pin clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ;the new prescaler ;move value and ccp on movwf ccp1con ;load ccp1con with this ;value ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: ? clear tmr1h and tmr1l registers ? not set interrupt flag bit tmr1f (pir1<0>) ? (for ccp2 only) set the go/done bit (adcon0<2>)
pic16cr7x ds21993c-page 56 ? 2007 microchip technology inc. 8.4.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an output by clearing the trisc<2> bit. 8.4.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 8.4.3 software interrupt mode when generate software interrupt mode is chosen, the ccp1 pin is not affected. the ccp1if or ccp2if bit is set, causing a ccp interrupt (if enabled). 8.4.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output of ccp2 resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). table 8-3: registers associated with capture, compare and timer1 note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the portc i/o data latch. note: the special event trigger from the ccp1 and ccp2 modules will not set interrupt flag bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ?ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ?ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1c kps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by capture and timer1. note 1: the psp is not implemented on the pic16cr73/76; always maintain these bits clear.
? 2007 microchip technology inc. ds21993c-page 57 pic16cr7x 8.5 pwm mode (pwm) in pulse width modulation mode, the ccpx pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 8-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 8.5.3 ?setup for pwm operation? . figure 8-3: simplified pwm block diagram a pwm output (figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 8-4: pwm output 8.5.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula: pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 8.5.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the formula: note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (1) rq s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 (note 1) note 1: the 8-bit timer is concatenated with the 2-bit inter- nal q clock or the 2 bits of the prescaler to create the 10-bit time base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 tmr2 reset tmr2 reset note: the timer2 postscaler (see section 8.3 ?capture mode? ) is not used in the deter- mination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? t osc ? (tmr2 prescale value) log ( f pwm log(2) f osc ) bits = resolution
pic16cr7x ds21993c-page 58 ? 2007 microchip technology inc. 8.5.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 regis- ter. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 8-4: example pwm frequencies and resolutions (f osc = 20 mhz) table 8-5: registers associated with pwm and timer2 pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ?ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ?ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 module register 0000 0000 0000 0000 92h pr2 timer2 module period register 1111 1111 1111 1111 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2c kps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by pwm and timer2. note 1: bits pspie and pspif are reserved on the pic16cr73/76; always maintain these bits clear.
? 2007 microchip technology inc. ds21993c-page 59 pic16cr7x 9.0 synchronous serial port (ssp) module 9.1 ssp module overview the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the ssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c) an overview of i 2 c operations and additional informa- tion on the ssp module can be found in the ? pic ? mid-range mcu family reference manual ? (ds33023). refer to application note an578, ? use of the ssp module in the i 2 c ? multi-master environment ? (ds00578). 9.2 spi mode this section contains register definitions and opera- tional characteristics of the spi module. additional information on the spi module can be found in the ? pic ? mid-range mcu family reference manual ? (ds33023). spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. to accomplish communication, typically three pins are used: ? serial data out (sdo) rc5/sdo ? serial data in (sdi) rc4/sdi/sda ? serial clock (sck) rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: ? slave select (ss ) ra5/ss /an4 when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and sspstat<7:6>. these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only)
pic16cr7x ds21993c-page 60 ? 2007 microchip technology inc. register 9-1: sspstat: sync serial port status (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 smp: spi data input sample phase bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time (microwire) spi slave mode: smp must be cleared when spi is used in slave mode i 2 c mode: this bit must be maintained clear bit 6 cke : spi clock edge select bit (figure 9-2, figure 9-3, and figure 9-4) spi mode, ckp = 0 : 1 = data transmitted on rising edge of sck (microwire alternate) 0 = data transmitted on falling edge of sck spi mode, ckp = 1 : 1 = data transmitted on falling edge of sck (microwire default) 0 = data transmitted on rising edge of sck i 2 c mode: this bit must be maintained clear bit 5 d/a : data/address bit (i 2 c? mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p : stop bit (i 2 c? mode only) this bit is cleared when the ssp module is dis abled, or when the start bit is detected last. sspen is cleared. 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s : start bit (i 2 c? mode only) this bit is cleared when the ssp module is dis abled, or when the stop bit is detected last. sspen is cleared. 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c? mode only) this bit holds the r/w bit information following the last addr ess match. this bit is only valid from the address match to the next start bit, stop bit, or ack bit. 1 = read 0 = write bit 1 ua : update address bit (10-bit i 2 c? mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf : buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only): 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty
? 2007 microchip technology inc. ds21993c-page 61 pic16cr7x register 9-2: sspcon: sync seri al port control (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov : receive overflow indicator bit in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new recepti on (and transmission) is initiated by writing to the sspbuf register. 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode. sspov must be cleared in software in either mode. 0 = no overflow bit 5 sspen : synchronous serial port enable bit in spi mode: 1 = enables serial port and configures sck, sdo and sdi as serial port pins 0 = disables serial port and confi gures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as serial port pins 0 = disables serial port and confi gures these pins as i/o port pins in both modes, when enabled, these pins must be properly configured as input or output. bit 4 ckp : clock polarity select bit in spi mode: 1 = idle state for clock is a high level (microwire default) 0 = idle state for clock is a low level (microwire alternate) in i 2 c mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) bit 3-0 sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 = i 2 c? slave mode, 7-bit address 0111 = i 2 c? slave mode, 10-bit address 1011 = i 2 c? firmware controlled master mode (slave idle) 1110 = i 2 c? slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c? slave mode, 10-bit address with start and stop bit interrupts enabled
pic16cr7x ds21993c-page 62 ? 2007 microchip technology inc. figure 9-1: ssp block diagram (spi mode) to enable the serial port, ssp enable bit, sspen (sspcon<5>) must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon register, and then set bit sspen. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisc register) appropriately programmed. that is: ? sdi must have trisc<4> set ? sdo must have trisc<5> cleared ? sck (master mode) must have trisc<3> cleared ? sck (slave mode) must have trisc<3> set ?ss must have trisa<5> set and adcon must be configured such that ra5 is a digital i/o read write internal data bus rc4/sdi/sda rc5/sdo ra5/ss/an4 rc3/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit 0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl peripheral oe note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke = ? 1 ?, then the ss pin control must be enabled. 3: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = ? 0100 ?), the state of the ss pin can affect the state read back from the trisc<5> bit. the peripheral oe signal from the ssp module into portc controls the state that is read back from the trisc<5> bit (see section 4.3 ?portc and the trisc register? for information on portc). if read-modify-write instructions, such as bsf are performed on the trisc register while the ss pin is high, this will cause the trisc<5> bit to be set, thus disabling the sdo output.
? 2007 microchip technology inc. ds21993c-page 63 pic16cr7x figure 9-2: spi mode timing, master mode figure 9-3: spi mode timing (slave mode with cke = 0 ) sck (ckp = 0 , sdi (smp = 0 ) sspif bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdi (smp = 1 ) sck (ckp = 0 , sck (ckp = 1 , sck (ckp = 1 , sdo bit 7 bit 7 bit 0 bit 0 cke = 0 ) cke = 1 ) cke = 0 ) cke = 1 ) sck (ckp = 0 ) sdi (smp = 0 ) sspif bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sck (ckp = 1 ) sdo bit 7 bit 0 ss (optional)
pic16cr7x ds21993c-page 64 ? 2007 microchip technology inc. figure 9-4: spi mode timing (slave mode with cke = 1 ) table 9-1: registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh. 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the ssp in spi mode. note 1: bits pspie and pspif are reserved on the pic16cr73/76; always maintain these bits clear. sck (ckp = 0) sdi (smp = 0) sspif bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sck (ckp = 1) sdo bit 7 bit 0 ss
? 2007 microchip technology inc. ds21993c-page 65 pic16cr7x 9.3 ssp i 2 c? operation the ssp module in i 2 c mode fully implements all slave functions except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. the ssp module implements the standard mode specifica- tions as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/ sck/scl pin, which is the clock (scl), and the rc4/ sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisc<4:3> bits. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). figure 9-5: ssp block diagram (i 2 c? mode) the ssp module has five registers for i 2 c operation. these are the: ? ssp control register (sspcon) ? ssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? ssp shift register (sspsr) ? not directly accessible ? ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled to support firmware master mode ?i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled to support firmware master mode ?i 2 c start and stop bit interrupts enabled to support firmware master mode, slave is idle selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. pull-up resistors must be provided externally to the scl and sda pins for proper operation of the i 2 c module. additional information on ssp i 2 c operation can be found in the ? pic ? mid-range mcu family reference manual ? (ds33023). 9.3.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this ack pulse. they include (either or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the overflow bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 9-2 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the overflow condi- tion. flag bit bf is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirements of the ssp module, are shown in timing parameter #100 and parameter #101. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg ) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda
pic16cr7x ds21993c-page 66 ? 2007 microchip technology inc. 9.3.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>) is set (interrupt is generated if enabled) ? on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave (figure 9-7). the five most sig- nificant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the sec- ond address byte. for a 10-bit address, the first byte would equal ? 1111 0 a9 a8 0 ?, where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf and ua are set). 5. update the sspadd register with the first (high) byte of address, if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. table 9-2: data transfer received byte actions 9.3.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspstat<0>) is set, or bit sspov (sspcon<6>) is set. this is an error condition due to the user?s firmware. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. status bits as data transfer is received sspsr sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 yes yes yes 10 no no yes 11 no no yes 0 1 no no yes note: shaded cells show the conditions where the user software did not properly clear the overflow condition.
? 2007 microchip technology inc. ds21993c-page 67 pic16cr7x figure 9-6: i 2 c? waveforms for reception (7-bit address) 9.3.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit, and pin rc3/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. then, pin rc3/sck/scl should be enabled by set- ting bit ckp (sspcon<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretch- ing the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 9-7). an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software and the sspstat register is used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. when the ack is latched by the slave, the slave logic is reset (resets sspstat register) and the slave then monitors for another occur- rence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then pin rc3/ sck/scl should be enabled by setting bit ckp. figure 9-7: i 2 c? waveforms for transmission (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent. sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written to before the ckp bit can be set)
pic16cr7x ds21993c-page 68 ? 2007 microchip technology inc. 9.3.2 master mode master mode of operation is supported in firmware using interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is dis- abled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master mode, the scl and sda lines are manipu- lated by clearing the corresponding trisc<4:3> bit(s). the output level is always low, irrespective of the value(s) in portc<4:3>. so when transmitting data, a ? 1 ? data bit must have the trisc<4> bit set (input) and a ? 0 ? data bit must have the trisc<4> bit cleared (out- put). the same scenario is true for the scl line with the trisc<3> bit. pull-up resistors must be provided externally to the scl and sda pins for proper operation of the i 2 c module. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt will occur if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received master mode of operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ), or with the slave active. when both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. 9.3.3 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions, allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisc<4:3>). there are two stages where this arbitration can be lost, these are: ? address transfer ? data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address trans- fer stage, communication to the device may be in progress. if addressed, an ack pulse will be gener- ated. if arbitration was lost during the data transfer stage, the device will need to retransfer the data at a later time. table 9-3: registers associated with i 2 c? operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c? mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp (2) cke (2) d/a psr/w ua bf 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by ssp module in i 2 c? mode. note 1: pspif and pspie are reserved on the pic16cr73/76; always maintain these bits clear. 2: maintain these bits clear in i 2 c mode.
? 2007 microchip technology inc. ds21993c-page 69 pic16cr7x 10.0 universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial communications interface or sci.) the usart can be configured as a full duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the usart can be configured in the following modes: ? asynchronous (full duplex) ? synchronous ? master (half duplex) ? synchronous ? slave (half duplex) bit spen (rcsta<7>) and bits trisc<7:6> have to be set in order to configure pins rc6/tx/ck and rc7/ rx/dt as the universal synchronous asynchronous receiver transmitter. register 10-1: txsta: transmit status and control (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode: don?t care synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh : high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be parity bit
pic16cr7x ds21993c-page 70 ? 2007 microchip technology inc. register 10-2: rcsta: receive status and control (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r-0 r-x spen rx9 sren cren ? ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port enabled (configures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode: don?t care synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care bit 4 cren : continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 unimplemented: read as ? 0 ? bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data can be parity bit (parity to be calculated by firmware)
? 2007 microchip technology inc. ds21993c-page 71 pic16cr7x 10.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 10-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 10-1. from this, the error in baud rate can be determined. it may be advantageous to use the high baud rate (brgh = 1 ), even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 10.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. table 10-1: baud rate formula table 10-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate = f osc /(16(x+1)) n/a x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the brg.
pic16cr7x ds21993c-page 72 ? 2007 microchip technology inc. table 10-3: baud rates for asynchronous mode (brgh = 0 ) baud rate f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz baud % error spbrg value (decimal) baud % error spbrg value (decimal) baud % error spbrg value (decimal) 1200 1,221 1.73% 255 1,202 0.16% 207 1,202 0.16% 129 2400 2,404 0.16% 129 2,404 0.16% 103 2,404 0.16% 64 9600 9,470 -1.36% 32 9,615 0.16% 25 9,766 1.73% 15 19,200 19,531 1.73% 15 19,231 0.16% 12 19,531 1.73% 7 38,400 39,063 1.73% 7 35,714 -6.99% 6 39,063 1.73% 3 57,600 62,500 8.51% 4 62,500 8.51% 3 52,083 -9.58% 2 76,800 78,125 1.73% 3 83,333 8.51% 2 78,125 1.73% 1 96,000 104,167 8.51% 2 83,333 -13.19% 2 78,125 -18.62% 1 115,200 104,167 -9.58% 2 125,000 8.51% 1 78,125 -32.18% 1 250,000 312,500 25.00% 0 250,000 0.00% 0 156,250 -37.50% 0 baud rate f osc = 4 mhz f osc = 3.6864 mhz f osc = 3.579545 mhz baud % error spbrg value (decimal) baud % error spbrg value (decimal) baud % error spbrg value (decimal) 300 300 0.16% 207 300 0.00% 191 301 0.23% 185 1200 1,202 0.16% 51 1,200 0.00% 47 1,190 -0.83% 46 2400 2,404 0.16% 25 2,400 0.00% 23 2,432 1.32% 22 9600 8,929 -6.99% 6 9,600 0.00% 5 9,322 -2.90% 5 19,200 20,833 8.51% 2 19,200 0.00% 2 18,643 -2.90% 2 38,400 31,250 -18.62% 1 28,800 -25.00% 1 27,965 -27.17% 1 57,600 62,500 8.51% 0 57,600 0.00% 0 55,930 -2.90% 0 76,800 62,500 -18.62% 0 ?? ? ?? ? table 10-4: baud rates for asynchronous mode (brgh = 1 ) baud rate f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz baud % error spbrg value (decimal) baud % error spbrg value (decimal) baud % error spbrg value (decimal) 2400 ? ? ? ? ? ? 2,441 1.73% 255 9600 9,615 0.16% 129 9,615 0.16% 103 9,615 0.16% 64 19,200 19,231 0.16% 64 19,231 0.16% 51 18,939 -1.36% 32 38,400 37,879 -1.36% 32 38,462 0.16% 25 39,063 1.73% 15 57,600 56,818 -1.36% 21 58,824 2.12% 16 56,818 -1.36% 10 76,800 78,125 1.73% 15 76,923 0.16% 12 78,125 1.73% 7 96,000 96,154 0.16% 12 100,000 4.17% 9 89,286 -6.99% 6 115,200 113,636 -1.36% 10 111,111 -3.55% 8 125,000 8.51% 4 250,000 250,000 0.00% 4 250,000 0.00% 3 208,333 -16.67% 2 300,000 312,500 4.17% 3 333,333 11.11% 2 312,500 4.17% 1 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz f osc = 3.579545 mhz baud % error spbrg value (decimal) baud % error spbrg value (decimal) baud % error spbrg value (decimal) 1200 1,202 0.16% 207 1,200 0.00% 191 1,203 0.23% 185 2400 2,404 0.16% 103 2,400 0.00% 95 2,406 0.23% 92 9600 9,615 0.16% 25 9,600 0.00% 23 9,727 1.32% 22 19,200 19,231 0.16% 12 19,200 0.00% 11 18,643 -2.90% 11 38,400 35,714 -6.99% 6 38,400 0.00% 5 37,287 -2.90% 5 57,600 62,500 8.51% 3 57,600 0.00% 3 55,930 -2.90% 3 76,800 83,333 8.51% 2 76,800 0.00% 2 74,574 -2.90% 2 96,000 83,333 -13.19% 2 115,200 20.00% 1 111,861 16.52% 1 115,200 125,000 8.51% 1 115,200 0.00% 1 111,861 -2.90% 1 250,000 250,000 0.00% 0 230,400 -7.84% 0 223,722 -10.51% 0
? 2007 microchip technology inc. ds21993c-page 73 pic16cr7x 10.2 usart asynchronous mode in this mode, the usart uses standard non-return-to- zero (nrz) format (one start bit, eight or nine data bits, and one stop bit). the most common data format is 8- bits. an on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart transmits and receives the lsb first. the usart?s transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the following important elements: ? baud rate generator ? sampling circuit ? asynchronous transmitter ? asynchronous receiver 10.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 10-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data by firmware. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register, the txreg register is empty. one instruction cycle later, flag bit txif (pir1<4>) and flag bit trmt (txsta<1>) are set. the txif interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set, regardless of the state of enable bit txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. status bit trmt is a read-only bit, which is set one instruction cycle after the tsr register becomes empty, and is cleared one instruction cycle after the tsr register is loaded. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 10-2). the transmission can also be started by first loading the txreg register and then setting enable bit txen. normally, when transmission is first started, the tsr register is empty. at that point, transfer to the txreg register will result in an immedi- ate transfer to tsr, resulting in an empty txreg. a back-to-back transfer is thus possible (figure 10-3). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result, the rc6/tx/ck pin will revert to high-impendance. in order to select 9-bit transmission, transmit bit tx9 (txsta<6>) should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg register can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit may be loaded in the tsr register. note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif is cleared by loading txreg.
pic16cr7x ds21993c-page 74 ? 2007 microchip technology inc. figure 10-1: usart transmit block diagram steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh ( section 10.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts transmission). 8. if using interrupts, ensure that gie and peie in the intcon register are set. figure 10-2: asynchronous master transmission txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ? word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag)
? 2007 microchip technology inc. ds21993c-page 75 pic16cr7x figure 10-3: asynchronous mast er transmission (back-to-back) table 10-5: registers associated with asynchronous transmission 10.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 10-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate, or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift register (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, flag bit rcif (pir1<5>) is set. the actual interrupt can be enabled/disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read-only bit which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double buffered register (i.e., it is a two-deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full, the overrun error bit oerr (rcsta<1>) will be set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in soft- ware. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhib- ited and no further data will be received, therefore, it is essential to clear error bit oerr if it is set. framing error bit ferr (rcsta<2>) is set if a stop bit is detected as clear. bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg will load bits rx9d and ferr with new values, therefore, it is essential for the user to read the rcsta register before reading rcreg register, in order not to lose the old ferr and rx9d information. address name b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. note 1: bits pspie and pspif are reserved on the pic16cr73/76; always maintain these bits clear. transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows tw o consecutive transmissions.
pic16cr7x ds21993c-page 76 ? 2007 microchip technology inc. figure 10-4: usart receive block diagram figure 10-5: asynchronous reception steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh ( section 10.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie is set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that gie and peie in the intcon register are set. x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? f osc 64 16 or start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. an overrun error indicates an error in user firmware.
? 2007 microchip technology inc. ds21993c-page 77 pic16cr7x table 10-6: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on the pic16cr73/76 devices; always maintain these bits clear.
pic16cr7x ds21993c-page 78 ? 2007 microchip technology inc. 10.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition, enable bit spen (rcsta<7>) is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 10.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 10-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cycle ), the txreg is empty and inter- rupt bit txif (pir1<4>) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set, regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. trmt is a read- only bit, which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the first data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is stable around the falling edge of the synchronous clock (figure 10-6). the transmission can also be started by first loading the txreg register and then setting bit txen (figure 10-7). this is advantageous when slow baud rates are selected, since the brg is kept in reset when bits txen, cren and sren are clear. setting enable bit txen will start the brg, creating a shift clock immediately. normally, when transmission is first started, the tsr register is empty, so a transfer to the txreg register will result in an immediate transfer to tsr, resulting in an empty txreg. back-to-back transfers are possible. clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to high- impendance. if either bit cren or bit sren is set during a transmission, the transmission is aborted and the dt pin reverts to a high-impendance state (for a reception). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic, however, is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear bit txen. if bit sren is set (to interrupt an on-going trans- mission and receive a single word), then after the single word is received, bit sren will be cleared and the serial port will revert back to transmitting, since bit txen is still set. the dt line will immediately switch from high-impendance receive mode to transmit and start driving. to avoid this, bit txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ?new? tx9d, the ?present? value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate ( section 10.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and peie in the intcon register are set.
? 2007 microchip technology inc. ds21993c-page 79 pic16cr7x figure 10-6: synchronous transmission figure 10-7: synchronous tran smission (through txen) table 10-7: registers associated with synchronous master transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. note 1: bits pspie and pspif are reserved on the pic16cr73/76 devices; always maintain these bits clear. bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck write to txreg reg txif bit (interrupt flag) trmt txen bit ? 1 ? ?1? note: sync master mode; spbrg = 0 . continuous transmission of two 8-bit words. word 2 trmt bit write word 1 write word 2 pin pin rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit
pic16cr7x ds21993c-page 80 ? 2007 microchip technology inc. 10.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>), or enable bit cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the recep- tion is continuous until cren is cleared. if both bits are set, cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt flag bit rcif (pir1<5>) is set. the actual interrupt can be enabled/ disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read-only bit, which is reset by the hardware. in this case, it is reset when the rcreg register has been read and is empty. the rcreg is a double buffered register (i.e., it is a two- deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full, then overrun error bit oerr (rcsta<1>) is set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited, so it is essential to clear bit oerr if it is set. the ninth receive bit is buffered the same way as the receive data. reading the rcreg register will load bit rx9d with a new value, therefore, it is essential for the user to read the rcsta register before reading rcreg, in order not to lose the old rx9d information. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate ( section 10.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that gie and peie in the intcon register are set. figure 10-8: synchronous rece ption (master mode, sren) cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brg = 0. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4
? 2007 microchip technology inc. ds21993c-page 81 pic16cr7x table 10-8: registers associated with synchronous master reception 10.4 usart synchronous slave mode synchronous slave mode differs from the master mode, in that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 10.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit when the master device drives the ck line. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). follow these steps when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and peie in the intcon register are set. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive data register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. note 1: bits pspie and pspif are reserved on the pic16cr73/76 devices; always maintain these bits clear.
pic16cr7x ds21993c-page 82 ? 2007 microchip technology inc. table 10-9: registers associated with synchronous slave transmission 10.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. bit sren is a ?don?t care? in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr reg- ister will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). follow these steps when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is complete and an interrupt will be generated, if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that gie and peie in the intcon register are set. table 10-10: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit data register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on the pic16cr73/76 devices; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive data register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on the pic16cr73/76 devices, always maintain these bits clear.
? 2007 microchip technology inc. ds21993c-page 83 pic16cr7x 11.0 analog-to-digital converter (a/d) module the 8-bit analog-to-digital (a/d) converter module has five inputs for the pic16cr73/76 and eight for the pic16cr74/77. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog reference voltage is software selectable to either the device?s positive supply voltage (v dd ), or the voltage level on the ra3/an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the a/d module has three registers. these registers are: ? a/d result register ((adres) ? a/d control register 0 (adcon0) ? a/d control register 1 ((adcon1) the adcon0 register, shown in register 11-1, controls the operation of the a/d module. the adcon1 register, shown in register 11-2, configures the functions of the port pins. the port pins can be configured as analog inputs (ra3 can also be a voltage reference), or as digital i/o. additional information on using the a/d module can be found in the ? pic ? mid-range mcu family reference manual ? (ds33023) and in application note an546, ? using the analog-to-digital converter ? (ds00546). register 11-1: adcon0: (address 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 adcs1:adcs0: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from the internal a/d module rc oscillator) bit 5-3 chs2:chs0 : analog channel select bits 000 = channel 0 (ra0/an0) 001 = channel 1 (ra1/an1) 010 = channel 2 (ra2/an2) 011 = channel 3 (ra3/an3) 100 = channel 4 (ra5/an4) 101 = channel 5 (re0/an5) (1) 110 = channel 6 (re1/an6) (1) 111 = channel 7 (re2/an7) (1) bit 2 go/done : a/d conversion status bit if adon = 1 : 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 =a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1 unimplemented : read as ? 0 ? bit 0 adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shut-off and consumes no operating current note: a/d channels 5, 6 and 7 are implemented on the pic16cr74/77 only.
pic16cr7x ds21993c-page 84 ? 2007 microchip technology inc. register 11-2: adcon1: (address 1fh) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ?pcfg2pcfg1pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented : read as ? 0 ? bit 2-0 pcfg2:pcfg0 : a/d port configuration control bits note 1: re0, re1 and re2 are implemented on the pic16cr74/77 only. a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra5 ra3 re0 (1) re1 (1) re2 (1) v ref 000 aaaaaaaav dd 001 aaaav ref aaara3 010 aaaaadddv dd 011 aaaav ref dddra3 100 aaddadddv dd 101 aaddv ref dddra3 11x ddddddddv dd
? 2007 microchip technology inc. ds21993c-page 85 pic16cr7x the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference and digital i/o (adcon1) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure the a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set peie bit ? set gie bit 3. select an a/d input channel (adcon0). 4. wait for at least an appropriate acquisition period. 5. start conversion: ? set go/done bit (adcon0) 6. wait for the a/d conversion to complete, by either: ? polling for the go/done bit to be cleared (interrupts disabled) or ? waiting for the a/d interrupt 7. read a/d result register (adres) and clear bit adif if required. 8. for next conversion, go to step 3 or step 4, as required. figure 11-1: a/d block diagram (input voltage) v in v ref (reference voltage) v dd pcfg2:pcfg0 chs2:chs0 000 or 010 or 100 or 001 or 011 or 101 re2/an7 (1) re1/an6 (1) re0/an5 (1) ra5/an4 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 111 110 101 100 011 010 001 000 a/d converter note 1: not available on pic16cr73/76 . 11x
pic16cr7x ds21993c-page 86 ? 2007 microchip technology inc. 11.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 11-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 11-2. the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 10 k . after the analog input channel is selected (changed), the acquisition period must pass before the conversion can be started. to calculate the minimum acquisition time, t acq , see the ? pic ? mid-range mcu family reference manual ? (ds33023). in general, however, given a maximum source impedance of 10 k and at a temperature of 100c, t acq will be no more than 16 sec. figure 11-2: analog input model table 11-1: t ad vs. maximum device operating frequencies (standard devices (c)) ad clock source (t ad ) maximum device frequency operation adcs1:adcs0 max. 2t osc 00 1.25 mhz 8t osc 01 5 mhz 32t osc 10 20 mhz rc (1, 2, 3) 11 (note 1) note 1: the rc source has a typical t ad time of 4 s but can vary between 2-6 s. 2: when the device frequencies are greater than 1 mhz, the rc a/d conversion clock source is only recommended for sleep operation. 3: for extended voltage devices (lc), please refer to the electrical specifications section. c pin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ) v dd = 51.2 pf 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
? 2007 microchip technology inc. ds21993c-page 87 pic16cr7x 11.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.0 t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the four possible options for t ad are: ?2 t osc (f osc /2) ?8 t osc (f osc /8) ?32 t osc (f osc /32) ? internal rc oscillator (2-6 s) for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time as small as possible, but no less than 1.6 s. 11.3 configuring analog port pins the adcon1, trisa and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. 11.4 a/d conversions setting the go/done bit begins an a/d conversion. when the conversion completes, the 8-bit result is placed in the adres register, the go/done bit is cleared, and the adif flag (pir<6>) is set. if both the a/d interrupt bit adie (pie1<6>) and the peripheral interrupt enable bit peie (intcon<6>) are set, the device will wake from sleep whenever adif is set by hardware. in addition, an interrupt will also occur if the global interrupt bit gie (intcon<7>) is set. clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be changed and the adif flag will not be set. after the go/done bit is cleared at either the end of a conversion, or by firmware, another conversion can be initiated by setting the go/done bit. users must still take into account the appropriate acquisition time for the application. 11.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared, and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d module will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 11.6 effects of a reset a device reset forces all registers to their reset state. the a/d module is disabled and any conversion in progress is aborted. all a/ d input pins are configured as analog inputs. the adres register will contain unknown data after a power-on reset. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the digital input buffer to consume current that is out of the device?s specification. note: the go/done bit should not be set in the same instruction that turns on the a/d. note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, ensure the sleep instruction immediately follows the instruc- tion that sets the go/done bit.
pic16cr7x ds21993c-page 88 ? 2007 microchip technology inc. 11.7 use of the ccp trigger an a/d conversion can be started by the ?special event trigger? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and an appropriate acquisi- tion time should pass before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?special event trigger? will be ignored by the a/d module, but will still reset the timer1 counter. table 11-2: summary of a/d registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ?ccp2ie ---- ---0 ---- ---0 1eh adres a/d result register byte xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 0000 00-0 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 09h porte (2) ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 89h trise (2) ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: bits pspie and pspif are reserved on the pic16cr73/76; always maintain these bits clear. 2: these registers are reserved on the pic16cr73/76.
? 2007 microchip technology inc. ds21993c-page 89 pic16cr7x 12.0 special features of the cpu these devices have a host of features intended to max- imize system reliability, minimize cost through elimina- tion of external components, provide power saving operating modes and offer code protection. these are: ? oscillator selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming? these devices have a watchdog timer, which can be enabled or disabled, using a configuration bit. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscil- lator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. it is designed to keep the part in reset while the power supply stabilizes, and is enabled or disabled, using a configuration bit. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low-current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. configuration bits are used to select the desired oscillator mode. additional information on special features is avail- able in the ? pic ? mid-range mcu family reference manual ? (ds33023). 12.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped in program memory location 2007h. the user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming.
pic16cr7x ds21993c-page 90 ? 2007 microchip technology inc. register 12-1: configuration word: (address 2007h (1) ) u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? bit 13 bit 7 r/p-1 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 boren ? cp0 pwrten wdten fosc1 fosc0 bit 6 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-7 unimplemented: read as ? 1 ? bit 6 boren : brown-out reset enable bit 1 = bor enabled 0 = bor disabled bit 5 unimplemented: read as ? 1 ? bit 4 cp0: rom program memory code protection bit 1 = code protection off 0 = all memory locations code protected bit 3 pwrten : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 2 wdten : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: the erased (unprogrammed) value of the configuration word is 3fffh.
? 2007 microchip technology inc. ds21993c-page 91 pic16cr7x 12.2 oscillator configurations 12.2.1 oscillator types the pic16cr7x can be operated in four different oscil- lator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low-power crystal ? xt crystal/resonator ? hs high-speed crystal/resonator ? rc resistor/capacitor 12.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 12-1). the pic16cr7x oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. when in hs mode, the device can accept an external clock source to drive the osc1/clkin pin (figure 12-2). see figu re 15-1 or figure 15-2 (depending on the part number and v dd range) for valid external clock frequencies. figure 12-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 12-2: external clock input operation (hs osc configuration) table 12-1: ceramic resonators (for design guidance only) note 1: see table 12-1 and table 12-2 for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16cr7x rs (2) internal typical capacitor values used: mode freq. osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 56 pf 47 pf 33 pf 56 pf 47 pf 33 pf hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf 22 pf capacitor values are for design guidance only. these capacitors were tested with the resonators listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes at the bottom of page 92 for additional information. resonators used: 455 khz panasonic efo-a455k04b 2.0 mhz murata erie csa2.00mg 4.0 mhz murata erie csa4.00mg 8.0 mhz murata erie csa8.00mt 16.0 mhz murata erie csa16.00mx osc1 osc2 open clock from ext. system pic16cr7x (hs mode)
pic16cr7x ds21993c-page 92 ? 2007 microchip technology inc. table 12-2: capacitor selection for crystal oscillator (for design guidance only) 12.2.3 rc oscillator for timing insensitive applications, the ?rc? device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the differ- ence in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 12-3 shows how the r/c combination is connected to the pic16cr7x. figure 12-3: rc oscillator mode osc type crystal freq. typical capacitor values tested: c1 c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 56 pf 56 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15 pf 15 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. these capacitors were tested with the crystals listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. crystals used: 32 khz epson c-001r32.768k-a 200 khz std xtl 200.000khz 1 mhz ecs ecs-10-13-1 4 mhz ecs ecs-40-20-1 8 mhz epson ca-301 8.000m-c 20 mhz epson ca-301 20.000m-c note 1: higher capacitance increases the stability of oscillator, but also increases the start- up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents. 3: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: always verify oscillator performance over the v dd and temperature range that is expected for the application. osc2/clkout c ext r ext pic16cr7x osc1 f osc /4 internal clock v dd v ss recommended values: 3 k r ext 100 k c ext > 20pf
? 2007 microchip technology inc. ds21993c-page 93 pic16cr7x 12.3 reset the pic16cr7x differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (during normal operation) ? wdt wake-up (during sleep) ? brown-out reset (bor) some registers are not affected in any reset condition. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep, and brown- out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differ- ently in different reset situations, as indicated in table 12-4. these bits are used in software to determine the nature of the reset. see table 12-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 12-4. figure 12-4: simplified block diagram of on-chip reset circuit s rq external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden (1)
pic16cr7x ds21993c-page 94 ? 2007 microchip technology inc. 12.4 mclr pic16cr7x devices have a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin has been altered from previous devices of this family. voltages applied to the pin that exceed its specification can result in both mclr resets and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 12-5, is suggested. figure 12-5: recommended mclr circuit 12.5 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v-1.7v). to take advantage of the por, tie the mclr pin to v dd as described in section 12.4 ?mclr? . a maximum rise time for v dd is specified. see the electrical specifica- tions for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607, ? power-up trouble shooting ? (ds00607). 12.6 power-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up only from the por. the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt?s time delay allows v dd to rise to an acceptable level. a configuration bit is provided to enable/disable the pwrt. the power-up time delay will vary from chip-to-chip, due to v dd , temperature and process variation. see dc parameters for details (t pwrt , parameter #33). 12.7 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscil- lator cycles (from osc1 input) delay after the pwrt delay is over (if enabled). this helps to ensure that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset, or wake-up from sleep. 12.8 brown-out reset (bor) the configuration bit, boden, can enable or disable the brown-out reset circuit. if v dd falls below v bor (parameter d005, about 4v) for longer than t bor (parameter #35, about 100 s), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer then keeps the device in reset for t pwrt (parameter #33, about 72 ms). if v dd should fall below v bor during t pwrt , the brown-out reset pro- cess will restart when v dd rises above v bor , with the power-up timer reset. the power-up timer is always enabled when the brown-out reset circuit is enabled, regardless of the state of the pwrt configuration bit. 12.9 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled) when a por reset occurs. then, ost starts counting 1024 oscillator cycles when pwrt ends (lp, xt, hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, all delays will expire. bringing mclr high will begin execution immediately. this is useful for testing purposes or to synchronize more than one pic16cr7x device operating in parallel. table 12-5 shows the reset conditions for the status, pcon and pc registers, while table 12-6 shows the reset conditions for all the registers. c1 0.1 f r1 1 k (or greater) (optional, not critical) v dd mclr pic16cr7x
? 2007 microchip technology inc. ds21993c-page 95 pic16cr7x 12.10 power control/status register (pcon) the power control/status register, pcon, has two bits to indicate the type of reset that last occurred. bit 0 is brown-out reset status bit, bor . bit bor is unknown on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a brown-out reset occurred. when the brown-out reset is disabled, the state of the bor bit is unpredictable. bit 1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. table 12-3: time-out in various situations table 12-4: status bits and their significance table 12-5: reset condition for special registers oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024 t osc 1024 t osc rc 72 ms ? 72 ms ? por (pcon<1>) bor (pcon<0>) to (status<4>) pd (status<3>) significance 0x 1 1 power-on reset 0x 0 x illegal, to is set on por 0x x 0 illegal, pd is set on por 10 1 1 brown-out reset 11 0 1 wdt reset 11 0 0 wdt wake-up 11 u u mclr reset during normal operation 11 1 0 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
pic16cr7x ds21993c-page 96 ? 2007 microchip technology inc. table 12-6: initialization conditions for all registers register devices power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt w 73747677 xxxx xxxx uuuu uuuu uuuu uuuu indf 73 74 76 77 n/a n/a n/a tmr0 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu pcl 73747677 0000h 0000h pc + 1 (2) status 73 74 76 77 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 73747677 xxxx xxxx uuuu uuuu uuuu uuuu porta 73747677 --0x 0000 --0u 0000 --uu uuuu portb 73747677 xxxx xxxx uuuu uuuu uuuu uuuu portc 73747677 xxxx xxxx uuuu uuuu uuuu uuuu portd 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu porte 73 74 76 77 ---- -xxx ---- -uuu ---- -uuu pclath 73 74 76 77 ---0 0000 ---0 0000 ---u uuuu intcon 73 74 76 77 0000 000x 0000 000u uuuu uuuu (1) pir1 73 74 76 77 r000 0000 r000 0000 ruuu uuuu (1) 73 74 76 77 0000 0000 0000 0000 uuuu uuuu (1) pir2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u (1) tmr1l 73747677 xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 73747677 xxxx xxxx uuuu uuuu uuuu uuuu t1con 73747677 --00 0000 --uu uuuu --uu uuuu tmr2 73 74 76 77 0000 0000 0000 0000 uuuu uuuu t2con 73747677 -000 0000 -000 0000 -uuu uuuu sspbuf 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu sspcon 73 74 76 77 0000 0000 0000 0000 uuuu uuuu ccpr1l 73747677 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 73747677 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 73 74 76 77 --00 0000 --00 0000 --uu uuuu rcsta 73 74 76 77 0000 -00x 0000 -00x uuuu -uuu txreg 73747677 0000 0000 0000 0000 uuuu uuuu rcreg 73 74 76 77 0000 0000 0000 0000 uuuu uuuu ccpr2l 73747677 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h 73747677 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 73 74 76 77 0000 0000 0000 0000 uuuu uuuu adres 73747677 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 73 74 76 77 0000 00-0 0000 00-0 uuuu uu-u option_reg 73 74 76 77 1111 1111 1111 1111 uuuu uuuu trisa 73747677 --11 1111 --11 1111 --uu uuuu trisb 73747677 1111 1111 1111 1111 uuuu uuuu trisc 73747677 1111 1111 1111 1111 uuuu uuuu trisd 73 74 76 77 1111 1111 1111 1111 uuuu uuuu trise 73 74 76 77 0000 -111 0000 -111 uuuu -uuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition, r = reserved, maintain clear note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 12-5 for reset value for specific condition.
? 2007 microchip technology inc. ds21993c-page 97 pic16cr7x figure 12-6: time-out sequence on power-up (mclr tied to v dd through rc network) pie1 73 74 76 77 r000 0000 r000 0000 ruuu uuuu 73 74 76 77 0000 0000 0000 0000 uuuu uuuu pie2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u pcon 73 74 76 77 ---- --qq ---- --uu ---- --uu pr2 73747677 1111 1111 1111 1111 1111 1111 sspstat 73 74 76 77 --00 0000 --00 0000 --uu uuuu sspadd 73747677 0000 0000 0000 0000 uuuu uuuu txsta 73747677 0000 -010 0000 -010 uuuu -uuu spbrg 73 74 76 77 0000 0000 0000 0000 uuuu uuuu adcon1 73 74 76 77 ---- -000 ---- -000 ---- -uuu pmdata 73 74 76 77 0--- 0000 0--- 0000 u--- uuuu pmadr 73747677 xxxx xxxx uuuu uuuu uuuu uuuu pmdath 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu pmadrh 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu pmcon1 73 74 76 77 1--- ---0 1--- ---0 1--- ---u table 12-6: initialization condition s for all registers (continued) register devices power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition, r = reserved, maintain clear note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 12-5 for reset value for specific condition. t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
pic16cr7x ds21993c-page 98 ? 2007 microchip technology inc. figure 12-7: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 12-8: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 12-9: slow rise time (mclr tied to v dd through rc network) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
? 2007 microchip technology inc. ds21993c-page 99 pic16cr7x 12.11 interrupts the pic16cr7x family has up to 12 sources of interrupt. the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. when bit gie is enabled and an interrupt?s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in various registers. individual interrupt bits are set, regardless of the status of the gie bit. the gie bit is cleared on reset. the ?return from interrupt? instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the special function registers, pir1 and pir2. the corre- sponding interrupt enable bits are contained in special function registers, pie1 and pie2, and the peripheral interrupt enable bit is contained in special function register, intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs, relative to the current q cycle. the latency is the same for one or two-cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, peie bit or the gie bit. figure 12-10: interrupt logic note: individual interrupt flag bits are set, regardless of the status of their corre- sponding mask bit or the gie bit. pspif (1) pspie (1) adif adie rcif rcie txif txie sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie tmr0if tmr0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu ccp2ie ccp2if note 1: psp interrupt is implemented only on pic16cr74/77 devices.
pic16cr7x ds21993c-page 100 ? 2007 microchip technology inc. 12.11.1 int interrupt external interrupt on the rb0/int pin is edge triggered, either rising, if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int inter- rupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie decides whether or not the processor branches to the interrupt vector following wake-up. see section 12.14 ?power-down mode (sleep)? for details on sleep mode. 12.11.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set flag bit tmr0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit tmr0ie (intcon<5>). ( section 5.0 ?timer0 module? ) 12.11.3 portb intcon change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<3>), see section 4.2 ?portb and the trisb register? . 12.12 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key registers during an interrupt (i.e., w, pclath and status registers). this will have to be implemented in software, as shown in example 12-1. for the pic16cr73/74 devices, the register w_temp must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 20h in bank 0, it must also be defined at a0h in bank 1.). the registers, pclath_temp and status_temp, are only defined in bank 0. since the upper 16 bytes of each bank are common in the pic16cr76/77 devices, temporary holding regis- ters w_temp, status_temp and pclath_temp should be placed in here. these 16 locations don?t require banking and, therefore, make it easier for context save and restore. the same code shown in example 12-1 can be used. example 12-1: saving status, w and pclath registers in ram movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page : :(isr) ;insert user code here : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
? 2007 microchip technology inc. ds21993c-page 101 pic16cr7x 12.13 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscillator, which does not require any external compo- nents. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status regis- ter will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing configuration bit, wdte ( section 12.1 ?configuration bits? ). wdt time-out period values may be found in the electrical specifications section under parameter #31. values for the wdt prescaler (actually a postscaler, but shared with the timer0 prescaler), may be assigned using the option_reg register. figure 12-11: watchdo g timer block diagram table 12-7: summary of watchdog timer registers note 1: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. 2: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) boren (1) ? cp0 pwrte n (1) wdten fosc1 fosc0 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see register 12-1 for operation of these bits. from tmr0 clock source (figure 5-1) to tmr0 (figure 5-1) postscaler wdt timer wdt enable bit 0 1 m u x psa 8-to-1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option_reg register. 8
pic16cr7x ds21993c-page 102 ? 2007 microchip technology inc. 12.14 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or high-impendance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are high-impendance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for low- est current consumption. the contribution from on-chip pull-ups on portb should also be considered. the mclr pin must be at a logic high level (v ihmc ). 12.14.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a ?wake-up?. the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred and caused wake-up. the following peripheral interrupts can wake the device from sleep: 1. psp read or write (pic16cr74/77 only). 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. ccp capture mode interrupt. 4. special event trigger (timer1 in asynchronous mode, using an external clock). 5. ssp (start/stop) bit detect interrupt. 6. ssp transmit or receive in slave mode (spi/i 2 c). 7. usart rx or tx (synchronous slave mode). 8. a/d conversion (when a/d clock source is rc). other peripherals cannot generate interrupts, since during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up occurs, regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt address (0004h). in cases where the execu- tion of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 12.14.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction.
? 2007 microchip technology inc. ds21993c-page 103 pic16cr7x figure 12-12: wake-up from sleep through interrupt 12.15 program verification/code protection if the code protection bit(s) have not been enabled, the on-chip program memory can be read out for verification purposes. 12.16 id locations four memory locations (2000h-2002h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are read- able for program verification. it is recommended that only the 4 least significant bits of the id location are used. 12.17 user code pic16cr7x microcontrollers are rom-based, thus user programming is not possible. please contact your microchip sales representitive for details on how to submit your final code. this information can also be found in application note an1010, ?pic16cr rom code submission process ?. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc + 2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = ? 1 ? assumed. in this case, after wake-up, th e processor jumps to the interrupt routine. if gie = ?0?, execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference.
pic16cr7x ds21993c-page 104 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21993c-page 105 pic16cr7x 13.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the formats for each of the categories are presented in figure 13-1, while the various opcode fields are summarized in table 13-1. table 13-2 lists the instructions recognized by the mpasm tm assembler. a complete description of each instruction is also available in the ? pic ? mid-range mcu family reference manual ? (ds33023). for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the w register. if ?d? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator, which selects the bit affected by the opera- tion, while ?f? represents the address of the file in which the bit is located. for literal and control operations, ?k? represents an eight- or eleven-bit constant or literal value. one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 13.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a ? clrf portb ? instruction will read portb, clear all the data bits, then write the result back to portb. this example would have the unin- tended result that the condition that sets the rbif flag would be cleared for pins configured as inputs and using the portb interrupt-on-change feature. table 13-1: opcode field descriptions figure 13-1: general format for instructions note: to maintain upward compatibility with future pic16cr7x products, do not use the option and tris instructions. field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1. pc program counter to time-out bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16cr7x ds21993c-page 106 ? 2007 microchip technology inc. table 13-2: pic16cr7x instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k ? k k k ? k ? ? k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input a nd is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tm r0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the ? pic ? mid-range mcu family reference manual ? (ds33023).
? 2007 microchip technology inc. ds21993c-page 107 pic16cr7x 13.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is 1 , the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruc- tion is discarded and a nop is executed instead, making this a 2t cy instruction. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b? in register ?f? is ? 0 ?, the next instruction is discarded and a nop is executed instead, making this a 2t cy instruction.
pic16cr7x ds21993c-page 108 ? 2007 microchip technology inc. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2007 microchip technology inc. ds21993c-page 109 pic16cr7x decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruc- tion is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruc- tion is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2t cy instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
pic16cr7x ds21993c-page 110 ? 2007 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register ?f? are moved to a destination dependant upon the status of ?d?. if ?d? = 0 , destination is w register. if ?d? = 1 , the destination is file register ?f? itself. ?d? = 1 is useful to test a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assemble as ? 0 ?s. movwf move w to f syntax: [ label ]movwf f operands: 0 f 127 operation: (w) (f) status affected: none description: move data from w register to register ?f?. nop no operation syntax: [ label ]nop operands: none operation: no operation status affected: none description: no operation. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2007 microchip technology inc. ds21993c-page 111 pic16cr7x rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. register f c register f c sleep syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit pd is cleared. time-out status bit to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic16cr7x ds21993c-page 112 ? 2007 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2007 microchip technology inc. advance information ds21993c-page 113 pic16cr7x 14.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 14.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic16cr7x ds21993c-page 114 advance information ? 2007 microchip technology inc. 14.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 14.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 family of microcontrollers and the dspic30, dspic33 and pic24 family of digital signal controllers. these compilers provide powerful integra- tion capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 14.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 14.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 14.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
? 2007 microchip technology inc. advance information ds21993c-page 115 pic16cr7x 14.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 14.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc ? and mcu devices. it debugs and programs pic ? and dspic ? flash microcontrollers with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 14.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 14.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
pic16cr7x ds21993c-page 116 advance information ? 2007 microchip technology inc. 14.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 14.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 14.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart ? battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) and the latest ?product selector guide? (ds00148) for the complete list of demonstration, development and evaluation kits.
? 2007 microchip technology inc. ds21993c-page 117 pic16cr7x 15.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... .-55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss ........................................................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................. -0.3 to +6.5v voltage on mclr with respect to v ss ...............................................................................................................0 to +5.5v voltage on ra4 with respect to vss ............................................................................................. .....................0 to +5.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb, and porte (combined) (note 3) ...................................................200 ma maximum current sourced by porta, portb, and porte (combined) (note 3) ..............................................200 ma maximum current sunk by portc and portd (combined) (note 3) .................................................................200 ma maximum current sourced by portc and portd (combined) (note 3) ............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes at the mclr pin may cause latch-up. a series resistor of greater than 1 k should be used to pull mclr to v dd , rather than tying the pin directly to v dd . 3: portd and porte are not implemented on the pic16cr73/76 devices. ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16cr7x ds21993c-page 118 ? 2007 microchip technology inc. figure 15-1: pic16cr7x voltage-frequency graph frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 20 mhz 5.0v 3.5v 3.0v 2.5v 16 mhz
? 2007 microchip technology inc. ds21993c-page 119 pic16cr7x 15.1 dc characteristics: pic16cr73/74/76/77 (industrial, extended) pic16cr73/74/76/77 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions v dd supply voltage d001 pic16cr7x 2.5 2.2 2.0 ? ? ? 5.5 5.5 5.5 v v v a/d in use, -40c to +85c a/d in use, 0c to +85c a/d not used, -40c to +85c d001 d001a pic16cr7x 4.0 v bor * ? ? 5.5 5.5 v v all configurations bor enabled (note 7) d002* v dr ram data retention voltage (note 1) ?1.5?v d003 v por v dd start voltage to ensure internal power-on reset signal ?v ss ? v see section on power-on reset for details d004* sv dd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section on power-on reset for details d005 v bor brown-out reset voltage 3.65 4.0 4.35 v boren bit in configuration word enabled legend: shading of rows is to assist in readability of of the table. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impendance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16cr7x ds21993c-page 120 ? 2007 microchip technology inc. i dd supply current (notes 2, 5) d010 d010a pic16cr7x ? ? 0.5 20 2 48 ma a xt, rc osc configuration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc configuration f osc = 32 khz, v dd = 3.0v, wdt disabled d010 d013 pic16cr7x ? ? 1.1 6.3 4 15 ma ma xt, rc osc configuration f osc = 4 mhz, v dd = 5.5v (note 4) hs osc configuration f osc = 20 mhz, v dd = 5.5v d015* i bor brown-out reset current (note 6) ?30200 a bor enabled, v dd = 5.0v d020 i pd power-down current (notes 3, 5) d021 pic16cr7x ? ? 2.0 0.1 30 5 a a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, -40 c to +85 c d020 d021 d021a pic16cr7x ? ? ? ? 5 0.1 10.5 1.5 42 19 57 42 a a a a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +85 c v dd = 4.0v, wdt enabled, -40 c to +125 c v dd = 4.0v, wdt disabled, -40 c to +125 c d023* i bor brown-out reset current (note 6) ?30200 a bor enabled, v dd = 5.0v 15.1 dc characteristics: pic16cr73/74/76/77 (industrial, extended) (continued) pic16cr73/74/76/77 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions legend: shading of rows is to assist in readability of of the table. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impendance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
? 2007 microchip technology inc. ds21993c-page 121 pic16cr7x 15.2 dc characteristics: pic16cr73/74/76/77 (industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification, section 15.1 ?dc characteristics: pic16cr73/74/76/77 (industrial, extended)? . param no. sym characteristic min typ? max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss ?0.15v dd v for entire v dd range d030a v ss ?0.8v v4.5v v dd 5.5v d031 with schmitt trigger buffer v ss ?0.2v dd v d032 mclr , osc1 (in rc mode) v ss ?0.2v dd v (note 1) d033 osc1 (in xt and lp mode) v ss ?0.3v v osc1 (in hs mode) v ss ?0.3v dd v v ih input high voltage i/o ports: d040 with ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d040a 0.25v dd + 0.8v ?v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd ?v dd v for entire v dd range d042 mclr 0.8v dd ?v dd v d042a osc1 (in xt and lp mode) 1.6v ? v dd v osc1 (in hs mode) 0.7v dd ?v dd v d043 osc1 (in rc mode) 0.9v dd ?v dd v (note 1) d070 i purb portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (notes 2, 3) d060 i/o ports ? ? 1 a vss v pin v dd , pin at high-impendance d061 mclr , ra4/t0cki ? ? 5 a vss v pin v dd d063 osc1 ? ? 5 a vss v pin v dd , xt, hs and lp osc configuration * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16cr7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16cr7x ds21993c-page 122 ? 2007 microchip technology inc. v ol output low voltage d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc config) ? ? ? ? 0.6 0.6 v v i ol = 1.6 ma, v dd = 4.5v, -40 c to +125 c i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c v oh output high voltage d090 i/o ports (note 3) v dd - 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc config) v dd - 0.7 v dd - 0.7 ? ? ? ? v v i oh = -1.3 ma, v dd = 4.5v, -40 c to +125 c i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* v od open drain high voltage ? ? 5.5 v ra4 pin capacitive loading specs on output pins d100 c osc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) ? ? 50 pf d102 c b scl, sda in i 2 c? mode ? ? 400 pf 15.2 dc characteristics: pic16cr73/74/76/77 (industrial, extended) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification, section 15.1 ?dc characteristics: pic16cr73/74/76/77 (industrial, extended)? . param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16cr7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2007 microchip technology inc. ds21993c-page 123 pic16cr7x 15.3 timing parameter symbology the timing parameter symbols have been created using one of the following formats: figure 15-2: load conditions 1. tpps2pps 3. t cc : st (i 2 c? specifications only) 2. tpps 4. ts (i 2 c? specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impendance) v valid l low z high-impendance i 2 c? only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 c l = 50 pf for all pins except osc2, but including portd and porte outputs as ports 15 pf for osc2 output note: portd and porte are not implemented on the pic16cr73/76 devices. load condition 1 load condition 2 legend:
pic16cr7x ds21993c-page 124 ? 2007 microchip technology inc. figure 15-3: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 15-1: external clock timing requirements parameter no. symbol characteristic min typ? max units conditions f osc external clkin frequency (note 1) dc ? 1 mhz xt osc mode dc ? 20 mhz hs osc mode dc ? 32 khz lp osc mode oscillator frequency (note 1) dc ? 4 mhz rc osc mode 0.1 ? 4 mhz xt osc mode 4 5 ? ? 20 200 mhz khz hs osc mode lp osc mode 1 t osc external clkin period (note 1) 1000 ? ? ns xt osc mode 50 ? ? ns hs osc mode 5? ?mslp osc mode oscillator period (note 1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 250 ns hs osc mode 5? ?mslp osc mode 2 t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3 to sl , to sh external clock in (osc1) high or low time 500 ? ? ns xt oscillator 2.5 ? ? ms lp oscillator 15 ? ? ns hs oscillator 4 to sr , to sf external clock in (osc1) rise or fall time ? ? 25 ns xt oscillator ? ? 50 ns lp oscillator ? ? 15 ns hs oscillator ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices.
? 2007 microchip technology inc. ds21993c-page 125 pic16cr7x figure 15-4: clko ut and i/o timing table 15-2: clkout and i/o timing requirements param no. symbol characteristic min typ? max units conditions 10* tosh2ckl osc1 to clkout ? 75 200 ns (note 1) 11* tosh2ckh osc1 to clkout ? 75 200 ns (note 1) 12* tckr clkout rise time ? 35 100 ns (note 1) 13* tckf clkout fall time ? 35 100 ns (note 1) 14* tckl2iov clkout to port out valid ? ? 0.5t cy + 20 ns (note 1) 15* tiov2ckh port in valid before clkout t osc + 200 ? ? ns (note 1) 16* tckh2ioi port in hold after clkout 0??ns (note 1) 17* tosh2iov osc1 (q1 cycle) to port out valid ? 100 255 ns 18* tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) standard ( 5v ) 100 ? ? ns extended ( 3v ) 200 ? ? ns 19* tiov2osh port input valid to osc1 (i/o in setup time) 0 ? ? ns 20* tior port output rise time standard ( 5v ) ? 10 40 ns extended ( 3v ) ? ? 145 ns 21* tiof port output fall time standard ( 5v ) ? 10 40 ns extended ( 3v ) ? ? 145 ns 22??* tinp int pin high or low time t cy ??ns 23??* trbp rb7:rb4 change int high or low time t cy ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events, not related to any internal clock edges. note 1: measurements are taken in rc mode, where clkout output is 4 x t osc . note: refer to figure 15-2 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16cr7x ds21993c-page 126 ? 2007 microchip technology inc. figure 15-5: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 15-6: brown-out reset timing table 15-3: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 ? ? sv dd = 5v, -40c to +85c 31* t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +85c 32 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33* t pwrt power-up timer period 28 72 132 ms v dd = 5v, -40c to +85c 34 t ioz i/o high-impendance from mclr low or watchdog timer reset ??2.1 s 35 t bor brown-out reset pulse width 100 ? ? sv dd v bor (d005) * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless other wise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 15-2 for load conditions. v dd v bor 35
? 2007 microchip technology inc. ds21993c-page 127 pic16cr7x figure 15-7: timer0 and timer1 external clock timings table 15-4: timer0 and timer1 external clock requirements param no. symbol characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 42* tt0p t0cki period no prescaler t cy + 40 ? ? ns with prescaler greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard( 5v )15??ns extended( 3v )25 ??ns asynchronous standard( 5v )30??ns extended( 3v )50 ??ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard( 5v )15??ns extended( 3v )25 ??ns asynchronous standard( 5v )30??ns extended( 3v )50 ??ns 47* tt1p t1cki input period synchronous standard( 5v ) greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) extended( 3v ) greater of: 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous standard( 5v )60??ns extended( 3v ) 100 ? ? ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note: refer to figure 15-2 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
pic16cr7x ds21993c-page 128 ? 2007 microchip technology inc. figure 15-8: capture/compare/pwm timings (ccp1 and ccp2) table 15-5: capture/compare/pwm requirements (ccp1 and ccp2) param no. symbol characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ? ? ns with prescaler standard( 5v )10??ns extended( 3v )20??ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ? ? ns with prescaler standard( 5v )10??ns extended( 3v )20??ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ? ? ns n = prescale value (1,4 or 16) 53* tccr ccp1 and ccp2 output rise time standard( 5v ) ? 10 25 ns extended( 3v ) ? 25 50 ns 54* tccf ccp1 and ccp2 output fall time standard( 5v ) ? 10 25 ns extended( 3v ) ? 25 45 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-2 for load conditions. and rc2/ccp1 (capture mode) 50 51 52 53 54 rc1/t1osi/ccp2 and rc2/ccp1 (compare or pwm mode) rc1/t1osi/ccp2
? 2007 microchip technology inc. ds21993c-page 129 pic16cr7x figure 15-9: parallel slave port timing (pic16cr74/77 devices only) table 15-6: parallel slave port requirements (pic16cr74/77 devices only) parameter no. symbol characteristic min typ? max units conditions 62 tdtv2wrh data in valid before wr or cs (setup time) 20 25 ? ? ? ? ns ns extended range only 63* twrh2dti wr or cs to data in invalid (hold time) standard( 5v )20 ? ? ns extended( 3v )35 ? ? ns 64 trdl2dtv rd and cs to data out valid ? ? ? ? 80 90 ns ns extended range only 65 trdh2dti rd or cs to data out invalid 10 ? 30 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-2 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
pic16cr7x ds21993c-page 130 ? 2007 microchip technology inc. figure 15-10: spi master mode timing (cke = 0 , smp = 0 ) figure 15-11: spi master mode timing (cke = 1 , smp = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 15-2 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 15-2 for load conditions.
? 2007 microchip technology inc. ds21993c-page 131 pic16cr7x figure 15-12: spi slave mode timing (cke = 0 ) figure 15-13: spi slave mode timing (cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in 83 note: refer to figure 15-2 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 74 75, 76 msb bit 6 - - - - - -1 lsb 77 msb in bit 6 - - - -1 lsb in 80 83 note: refer to figure 15-2 for load conditions.
pic16cr7x ds21993c-page 132 ? 2007 microchip technology inc. table 15-7: spi mode requirements figure 15-14: i 2 c? bus start/stop bits timing param no. symbol characteristic min typ? max units conditions 70* tssl2sch, ts s l 2 s c l ss to sck or sck input t cy ??ns 71* tsch sck input high time (slave mode) t cy + 20 ? ? ns 72* tscl sck input low time (slave mode) t cy + 20 ? ? ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ? ns 74* tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ? ns 75* tdor sdo data output rise time standard( f ) extended( lf ) ? ? 10 25 25 50 ns ns 76* tdof sdo data output fall time ? 10 25 ns 77* tssh2doz ss to sdo output high-impendance 10 ? 50 ns 78* tscr sck output rise time (master mode) standard( 5v ) extended( 3v ) ? ? 10 25 25 50 ns ns 79* tscf sck output fall time (master mode) ? 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge standard( 5v ) extended( 3v ) ? ? ? ? 50 145 ns ns 81* tdov2sch, tdov2scl sdo data output setup to sck edge tcy ? ? ns 82* tssl2dov sdo data output valid after ss edge ? ? 50 ns 83* tsch2ssh, ts c l 2 s s h ss after sck edge 1.5t cy + 40 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note : refer to figure 15-2 for load conditions. 91 92 93 scl sda start condition stop condition 90
? 2007 microchip technology inc. ds21993c-page 133 pic16cr7x table 15-8: i 2 c? bus start/stop bits requirements figure 15-15: i 2 c? bus data timing param no. symbol characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ? 91* t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? ? 92* t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? 93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? * these parameters are characterized but not tested. note: refer to figure 15-2 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16cr7x ds21993c-page 134 ? 2007 microchip technology inc. table 15-9: i 2 c? bus data requirements param. no. symbol characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? 101* t low clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? 102* t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91* t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? s 106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92* t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110* t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s c b bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
? 2007 microchip technology inc. ds21993c-page 135 pic16cr7x figure 15-16: usart synchronous transmission (master/slave) timing table 15-10: usart synchronous transmission requirements figure 15-17: usart synchronous receive (master/slave) timing table 15-11: usart synchronous receive requirements param no. symbol characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & slave) clock high to data out valid standard( 5v ) ? ? 80 ns extended( 3v )??100ns 121 tckrf clock out rise time and fall time (master mode) standard( 5v )??45ns extended( 3v )??50ns 122 tdtrf data out rise time and fall time standard( 5v )??45ns extended( 3v )??50ns ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. symbol characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & slave) data setup before ck (dt setup time) 15 ? ? ns 126 tckl2dtl data hold after ck (dt hold time) 15 ? ? ns ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-2 for load conditions. 121 121 122 rc6/tx/ck rc7/rx/dt pin pin 120 note: refer to figure 15-2 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin
pic16cr7x ds21993c-page 136 ? 2007 microchip technology inc. table 15-12: a/d converter characteristics:pic16cr7x (industrial, extended) param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 8 bits bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs total absolute error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 ? monotonicity (note 3) ? guaranteed ? ? v ss v ain v ref a20 v ref reference voltage 2.5 2.2 ? ? 5.5 5.5 v v -40c to +125c 0c to +125c a25 v ain analog input voltage v ss - 0.3 ? v ref + 0.3 v a30 z ain recommended impedance of analog voltage source ? ? 10.0 k a40 i ad a/d conversion current (v dd )? 180 ? a average current consumption when a/d is on (note 1) . a50 i ref v ref input current (note 2) n/a ? ? ? 5 500 a a during v ain acquisition. during a/d conversion cycle. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from the ra3 pin or the v dd pin, whichever is selected as a reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
? 2007 microchip technology inc. ds21993c-page 137 pic16cr7x figure 15-18: a/d conversion timing table 15-13: a/d conversion requirements param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period pic16cr7x 1.6 ? ? st osc based, v ref 3.0v pic16cr7x 2.0 ? ? st osc based, 2.0v v ref 5.5v pic16cr7x 2.0 4.0 6.0 s a/d rc mode pic16cr7x 3.0 6.0 9.0 s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 9?9t ad 132 t acq acquisition time 5* ? ? s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 11.1 ?a/d acquisition requirements? for minimum conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134
pic16cr7x ds21993c-page 138 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21993c-page 139 pic16cr7x 16.0 dc and ac characteristics graphs and tables ?typical? represents the mean of the distribution at 25 c. ?maximum? or ?minimum? represents (mean + 3 ) or (mean - 3 ) respectively, where is a standard deviation, over the whole temperature range. figure 16-1: typical i dd vs. f osc over v dd (hs mode) figure 16-2: maximum i dd vs. f osc over v dd (hs mode) note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0 1 2 3 4 5 6 7 4 6 8 101214161820 fos c(mhz) i dd(m a) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v 0 1 2 3 4 5 6 7 8 4 6 8 10 1214161820 fos c ( mhz ) i dd(m a) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v
pic16cr7x ds21993c-page 140 ? 2007 microchip technology inc. figure 16-3: typical i dd vs. f osc over v dd (xt mode) figure 16-4: maximum i dd vs. f osc over v dd (xt mode) 0 0.2 0.4 0.6 0.8 1 1. 2 0.5 11.52 2.533.54 fos c (mhz ) i dd (m a) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 0.511.522.533.54 fos c (mhz ) i dd(m a) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v
? 2007 microchip technology inc. ds21993c-page 141 pic16cr7x figure 16-5: typical i dd vs. f osc over v dd (lp mode) figure 16-6: maximum i dd vs. f osc over v dd (lp mode) 0 5 10 15 20 25 30 35 40 45 30 40 50 60 70 80 90 100 fos c ( khz ) i dd ( a) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 5.5v 5.0v 4.5v 4.0v 2.0v 15 25 35 45 55 65 75 85 30 40 50 60 70 80 90 100 fos c (khz ) idd (a) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 5.5v 5.0v 4.5v 4.0v 2.0v
pic16cr7x ds21993c-page 142 ? 2007 microchip technology inc. figure 16-7: average f osc vs. v dd for various values of r (rc mode, c = 20 pf, 25 c) figure 16-8: average f osc vs. v dd for various values of r (rc mode, c = 100 pf, 25 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.533.544.555.5 v dd ( v ) f req (mh z) operation above 4 mhz is not recommended 10 k 100 k 10k (f7x) 0 0.5 1 1.5 2 2.5 2.533.544.555.5 v dd ( v ) f req (mh z) 5.1 k 10 k 100 k 10k (f7x)
? 2007 microchip technology inc. ds21993c-page 143 pic16cr7x figure 16-9: average f osc vs. v dd for various values of r (rc mode, c = 300 pf, 25 c) figure 16-10: i pd vs. v dd (sleep mode, all peripherals disabled) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.5 3 3.5 4 4.5 5 5.5 vdd (v) f req (mh z) 3.3k 5.1k 10k 100k 10k (f7x) 0.01 0.1 1 10 100 2.02.53.03.54.04.55.05.5 v dd (v) i pd (ua) max 125c max 85c typ 25c typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c)
pic16cr7x ds21993c-page 144 ? 2007 microchip technology inc. figure 16-11: i bor vs. v dd over temperature figure 16-12: typical and maximum i wdt vs. v dd over temperature 10 100 1,000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v ) device in reset device in sleep indeterminant state max (125?c) typ (25?c) max (125?c) typ (25?c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) note: device current in reset depends on oscillator mode, frequency and circuit. i dd ( a) 0.1 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v ) max (125?c) typ (25?c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) i wdt ( a)
? 2007 microchip technology inc. ds21993c-page 145 pic16cr7x figure 16-13: typical, minimum and maximum wdt period vs. v dd (-40 c to 125 c) figure 16-14: average wdt period vs. v dd over temperature (-40 c to 125 c) 0 5 10 15 20 25 30 35 40 45 50 2.02.53.03.54.04.55.05.5 v dd (v) wdt period (ms) max (125c) typ (25c) min (-40c) 16f77 typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 0 5 10 15 20 25 30 35 40 45 50 2.02.53.03.54.04.55.05.5 v dd (v) wdt period (ms) 125c 85c 25c -40c typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c)
pic16cr7x ds21993c-page 146 ? 2007 microchip technology inc. figure 16-15: typical, minimum and maximum v oh vs. i oh (v dd = 5v, -40 c to 125 c) figure 16-16: typical, minimum and maximum v oh vs. i oh (v dd = 3v, -40 c to 125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 i oh (-ma) v oh (v) max typ (25c) min typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 i oh (-ma) v oh (v) max typ (25c) min typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c)
? 2007 microchip technology inc. ds21993c-page 147 pic16cr7x figure 16-17: typical, minimum and maximum v ol vs. i ol (v dd = 5v, -40 c to 125 c) figure 16-18: typical, minimum and maximum v ol vs. i ol (v dd = 3v, -40 c to 125 c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (125c) max (85c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (125c) max (85c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c)
pic16cr7x ds21993c-page 148 ? 2007 microchip technology inc. figure 16-19: minimum and maximum v in vs. v dd , (ttl input, -40 c to 125 c) figure 16-20: minimum and maximum v in vs. v dd (st input, -40 c to 125 c) 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v th max (-40c) v th min (125c) v th typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max (125c) v ih min (-40c) v il max (-40c) v il min (125c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to 125c) minimum: mean ? 3 (-40c to 125c)
? 2007 microchip technology inc. ds21993c-page 149 pic16cr7x 17.0 packaging information 17.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead pdip xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxxx example picxxfxxxx-i/p 0710017 40-lead pdip xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn example picxxfxxxx-i/p 0710017 44-lead plcc xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example picxxfxxx /l 0710017 3 e 3 e 3 e
pic16cr7x ds21993c-page 150 ? 2007 microchip technology inc. 17.1 package marking information (continued) 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example picxxfxxxx -i/pt 0710017 28-lead soic (.300?) xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example picxxfxxxx/so 0710017 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example picxxfxxxx -i/ss 0710017 28-lead qfn xxxxxxxx xxxxxxxx yywwnnn example xxfxxx /ml 0710017 3 e 3 e 3 e 3 e
? 2007 microchip technology inc. ds21993c-page 151 pic16cr7x 17.2 package details the following sections give the technical details of the packages. 28-lead skinny plastic dual in-line (sp) ? 300 mil body [spdip] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a ? ? .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 note 1 n 12 d e1 e b c e l a2 e b b1 a1 a 3 microchip technology drawing c04-070 b
pic16cr7x ds21993c-page 152 ? 2007 microchip technology inc. 40-lead plastic dual in-line (p) ? 600 mil body [pdip] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 40 pitch e .100 bsc top to seating plane a ? ? .250 molded package thickness a2 .125 ? .195 base to seating plane a1 .015 ? ? shoulder to shoulder width e .590 ? .625 molded package width e1 .485 ? .580 overall length d 1.980 ? 2.095 tip to seating plane l .115 ? .200 lead thickness c .008 ? .015 upper lead width b1 .030 ? .070 lower lead width b .014 ? .023 overall row spacing eb ? ? .700 n note 1 e1 d 12 3 a a1 b1 b e c e b e l a2 microchip technology drawing c04-016 b
? 2007 microchip technology inc. ds21993c-page 153 pic16cr7x 44-lead plastic leaded chip carrier (l) ? square [plcc] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4 . dimensioning and tolerancing per asme y14.5m. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 44 pitch e .050 overall height a .165 .172 .180 contact height a1 .090 .105 .120 molded package to contact a2 .062 ? .083 standoff a3 .020 ? ? corner chamfer ch1 .042 ? .048 chamfers ch2 ? ? .020 side chamfer ch3 .042 ? .056 overall width e .685 .690 .695 overall length d .685 .690 .695 molded package width e1 .650 .653 .656 molded package length d1 .650 .653 .656 footprint width e2 .582 .610 .638 footprint length d2 .582 .610 .638 lead thickness c .0075 ? .0125 upper lead width b1 .026 ? .032 lower lead width b .013 ? .021 ch2 x 45 ch1 x 45 ch 3 x 45 a1 a 3 e2 b1 b a a2 d2 e c note 1 n12 3 e e1 d d1 microchip technology drawing c04-048 b
pic16cr7x ds21993c-page 154 ? 2007 microchip technology inc. 28-lead plastic quad flat, no lead package (ml) ? 6x6 mm body [qfn] w ith 0.55 mm contact length n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . package is saw singulated. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 6.00 bsc exposed pad width e2 3.65 3.70 4.20 overall length d 6.00 bsc exposed pad length d2 3.65 3.70 4.20 contact width b 0.23 0.30 0.35 contact length l 0.50 0.55 0.70 contact-to-exposed pad k 0.20 ? ? d exposed d2 e b k e2 e l n note 1 1 2 2 1 n a a1 a 3 top view bottom view pad microchip technology drawing c04-105 b
? 2007 microchip technology inc. ds21993c-page 155 pic16cr7x 28-lead plastic small outline (so) ? wide, 7.50 mm body [soic] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millmeters dimension limits min nom max number of pins n 28 pitch e 1.27 bsc overall height a ? ? 2.65 molded package thickness a2 2.05 ? ? standoff a1 0.10 ? 0.30 overall width e 10.30 bsc molded package width e1 7.50 bsc overall length d 17.90 bsc chamfer (optional) h 0.25 ? 0.75 foot length l 0.40 ? 1.27 footprint l1 1.40 ref foot angle top 0 ? 8 lead thickness c 0.18 ? 0.33 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 c h h l l1 a2 a1 a note 1 12 3 b e e e1 d n microchip technology drawing c04-052 b
pic16cr7x ds21993c-page 156 ? 2007 microchip technology inc. 28-lead plastic shrink small outline (ss) ? 5.30 mm body [ssop] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.20 mm per side. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a ? ? 2.00 molded package thickness a2 1.65 1.75 1.85 standoff a1 0.05 ? ? overall width e 7.40 7.80 8.20 molded package width e1 5.00 5.30 5.60 overall length d 9.90 10.20 10.50 foot length l 0.55 0.75 0.95 footprint l1 1.25 ref lead thickness c 0.09 ? 0.25 foot angle 0 4 8 lead width b 0.22 ? 0.38 l l1 c a2 a1 a e e1 d n 1 2 note 1 b e microchip technology drawing c04-073 b
? 2007 microchip technology inc. ds21993c-page 157 pic16cr7x 44-lead plastic thin quad flatpack (pt) ? 10x10x1 mm body, 2.00 mm footprint [tqfp] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . chamfers at corners are optional; size may vary. 3 . dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 44 lead pitch e 0.80 bsc overall height a ? ? 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 ? 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 12.00 bsc overall length d 12.00 bsc molded package width e1 10.00 bsc molded package length d1 10.00 bsc lead thickness c 0.09 ? 0.20 lead width b 0.30 0.37 0.45 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 a e e1 d d1 e b note 1 note 2 n 12 3 c a1 l a2 l1 microchip technology drawing c04-076 b
pic16cr7x ds21993c-page 158 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21993c-page 159 pic16cr7x appendix a: revision history revision a (march 2006) this is a new data sheet. however, these devices are similar to the pic16f7x devices found in the pic16f7x data sheet (ds30325b). revision b (december 2006) revised 15.1 dc characteristics param. no. d005, d020, d021, d021a; 15.2 dc characteristics param. no. d070; table 15-3, param. no. 30. replaced pack- age drawings. revision c (january 2007) this revision includes updates to the packaging diagrams. appendix b: device differences the differences between the devices in this data sheet are listed in table b-1. table b-1: device differences difference pic16cr73 pic16cr74 pic16cr76 pic16cr77 rom program memory (14-bit words) 4k 4k 8k 8k data memory (bytes) 192 192 368 368 i/o ports 3 5 3 5 a/d 5 channels, 8 bits 8 channels, 8 bits 5 channels, 8 bits 8 channels, 8 bits parallel slave port no yes no yes interrupt sources 11121112 packages 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin tqfp 44-pin plcc 28-pin pdip 28-pin soic 28-pin ssop 28-pin mlf 40-pin pdip 44-pin tqfp 44-pin plcc
pic16cr7x ds21993c-page 160 ? 2007 microchip technology inc. appendix c: conversion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in table c-1. table c-1: conversion considerations characteristic pic16cr7x pic16f87x pic16f7x pins 28/40 28/40 28/40 timers 3 3 3 interrupts 11 or 12 13 or 14 11 or 12 communication psp, usart, ssp (spi, i 2 c? slave) psp, usart, ssp (spi, i 2 c master/slave) psp, usart, ssp (spi, i 2 c slave) frequency 20 mhz 20 mhz 20 mhz a/d 8-bit 10-bit 8-bit ccp 2 2 2 program memory 4k, 8k rom 4k, 8k flash (1,000 e/w cycles) 4k, 8k flash (100 e/w cycles, typical) ram 192, 368 bytes 192, 368 bytes 192, 368 bytes eeprom data none 128, 256 bytes none other ? in-circuit debugger, low-voltage programming ?
? 2007 microchip technology inc. ds21993c-page 161 pic16cr7x index a a/d a/d conversio status (go/done bit) ........................ 83 acquisition requirements ........................................... 86 adcon0 register....................................................... 83 adcon1 register....................................................... 83 adres register ......................................................... 83 analog port pins ......................................... 8, 10, 12, 39 analog-to-digital converter......................................... 83 associated registers .................................................. 88 configuring analog port pins...................................... 87 configuring the interrupt ............................................. 85 configuring the module............................................... 85 conversion clock........................................................ 87 conversion requirements ........................................ 137 conversions ................................................................ 87 converter characteristics ......................................... 136 effects of a reset ..................................................... 87 faster conversion ? lower resolution trade-off ....... 87 internal sampling switch (rss) impedance ................ 86 operation during sleep ............................................ 87 source impedance...................................................... 86 using the ccp trigger................................................ 88 absolute maximum ratings .............................................. 117 ack pulse ..................................................................... 65, 66 adcon0 register............................................................... 83 go/done bit.............................................................. 83 adcon1 register............................................................... 83 adres register ................................................................. 83 analog port pins. see a/d application notes an552 (implementing wake-up on key strokes using pic16f7x)............................................... 33 an556 (implementing a table read) ......................... 26 an578 (use of the ssp module in the i 2 c multi-master environment).................................. 59 an607 (power-up trouble shooting).......................... 94 assembler mpasm assembler................................................... 114 b banking, data memory ....................................................... 13 bf bit................................................................................... 60 block diagrams a/d .............................................................................. 85 analog input model ..................................................... 86 capture mode operation ............................................ 55 compare ..................................................................... 55 crystal/ceramic resonator operation (hs, xt or lp osc configuration) .................................... 91 external clock input operation (hs osc configuration)....................................... 91 interrupt logic ............................................................. 99 pic16cr73 and pic16cr76........................................ 6 pic16cr74 and pic16cr77........................................ 7 porta ra3:ra0 and ra5 port pins .............................. 31 ra4/t0cki pin ................................................... 31 portb rb3:rb0 port pins ............................................. 33 rb7:rb4 port pins ............................................. 33 portc (peripheral output override) ......................... 35 portd (in i/o port mode).......................................... 36 portd and porte (parallel slave port) .................. 40 porte (in i/o port mode) ......................................... 37 pwm mode................................................................. 57 rc oscillator mode .................................................... 92 recommended mclr circuit..................................... 94 reset circuit ............................................................... 93 ssp (i 2 c mode).......................................................... 65 ssp (spi mode) ......................................................... 62 timer0/wdt prescaler ............................................... 43 timer1 ........................................................................ 48 timer2 ........................................................................ 51 usart receive .............................................................. 76 usart transmit ........................................................ 74 watchdog timer (wdt)............................................ 101 bor. see brown-out reset brgh bit ............................................................................ 71 brown-out reset (bor).............................. 89, 93, 94, 95, 96 c c compilers mplab c18.............................................................. 114 mplab c30.............................................................. 114 capture/compare/pwm (ccp) associated registers............................................ 56, 58 capture mode............................................................. 55 prescaler ............................................................ 55 ccp pin configuration ......................................... 55, 56 ccp1 rc2/ccp1 pin................................................ 9, 11 ccp2 rc1/t1osi/ccp2 pin .................................... 9, 11 compare mode........................................................... 55 software interrupt mode ..................................... 56 special trigger output........................................ 56 timer1 mode selection....................................... 56 example pwm frequencies and resolutions ............ 58 interaction of two ccp modules................................ 53 pwm duty cycle ........................................................ 57 pwm mode................................................................. 57 pwm period ............................................................... 57 setup for pwm operation .......................................... 58 special event trigger and a/d conversions .............. 56 timer resources ........................................................ 53 ccp1 module ..................................................................... 53 ccp2 module ..................................................................... 53 ccpr1h register............................................................... 53 ccpr1l register ............................................................... 53 ccpxm<3:0> bits................................................................ 54 ccpxx and ccpxy bits...................................................... 54 cke bit ............................................................................... 60 ckp bit ............................................................................... 61 code examples call of a subroutine in page 1 from page 0 ............... 26 changing between capture prescalers ..................... 55 changing prescaler assignment to timer0 ................ 45 changing prescaler assignment to wdt ................... 45 indirect addressing..................................................... 27 initializing porta ...................................................... 31 reading a 16-bit free-running timer ........................ 49 rom program read................................................... 30 saving status, w, and pclath registers in ram............................................................. 100 writing a 16-bit free-running timer .......................... 49 code protection .......................................................... 89, 103
pic18fxxxx ds21993c-page 162 ? 2007 microchip technology inc. computed goto ................................................................ 26 configuration bits................................................................ 89 continuous receive enable (cren bit) ............................. 70 conversion considerations ............................................... 160 customer change notification service ............................. 167 customer notification service........................................... 167 customer support ............................................................. 167 d d/a bit ................................................................................. 60 data memory....................................................................... 13 bank select (rp1:rp0 bits) ....................................... 13 general purpose registers......................................... 13 register file map, pic16cr74/73.............................. 15 register file map, pic16cr77/76.............................. 14 special function registers ......................................... 16 data/address bit (d/a ) ........................................................ 60 dc and ac characteristics graphs and tables ................................................... 139 dc characteristics ............................................................ 119 development support ....................................................... 113 device differences ............................................................ 159 device overview ................................................................... 5 features ........................................................................ 5 direct addressing................................................................ 27 e electrical characteristics................................................... 117 errata .................................................................................... 4 external clock input (ra4/t0cki). see timer0 external interrupt input (rb0/int). see interrupt sources f firmware instructions........................................................ 105 fsr register....................................................................... 27 i i/o ports .............................................................................. 31 i 2 c mode addressing .................................................................. 66 associated registers .................................................. 68 master mode ............................................................... 68 mode selection ........................................................... 65 multi-master mode ...................................................... 68 operation .................................................................... 65 reception .................................................................... 66 slave mode scl and sda pins .............................................. 65 transmission............................................................... 67 id locations ...................................................................... 103 indf register ..................................................................... 27 indirect addressing ............................................................. 27 fsr register .............................................................. 13 instruction format ............................................................. 105 instruction set ................................................................... 105 addlw ..................................................................... 107 addwf ..................................................................... 107 andlw ..................................................................... 107 andwf ..................................................................... 107 bcf ........................................................................... 107 bsf ........................................................................... 107 btfsc ...................................................................... 107 btfss ...................................................................... 107 call ......................................................................... 108 clrf......................................................................... 108 clrw ....................................................................... 108 clrwdt .................................................................. 108 comf ....................................................................... 108 decf ........................................................................ 108 decfsz ................................................................... 109 goto ....................................................................... 109 incf ......................................................................... 109 incfsz..................................................................... 109 iorlw ...................................................................... 109 iorwf...................................................................... 109 return........................................................... 110, 111 rlf ........................................................................... 111 rrf .................................................................. 110, 111 sleep .............................................................. 110, 111 sublw ............................................................. 110, 111 subwf............................................................. 110, 111 swapf ..................................................................... 112 xorlw .................................................................... 112 xorwf .................................................................... 112 summary table ........................................................ 106 int interrupt (rb0/int). see interrupt sources intcon register................................................................ 21 gie bit ........................................................................ 21 inte bit ...................................................................... 21 intf bit ...................................................................... 21 rbif bit ................................................................ 21, 33 tmr0ie bit ................................................................. 21 inter-integrated circuit (i 2 c). see i 2 c mode internet address ............................................................... 167 interrupt sources .......................................................... 89, 99 interrupt-on-change (rb7:rb4) ................................. 33 rb0/int pin, external..................................... 8, 11, 100 tmr0 overflow......................................................... 100 usart receive/transmit complete .......................... 69 interrupts synchronous serial port interrupt............................... 23 interrupts, context saving during..................................... 100 interrupts, enable bits global interrupt enable (gie bit) .......................... 21, 99 interrupt-on-change (rb7:rb4) enable (rbie bit).. 100 rb0/int enable (inte bit) ......................................... 21 tmr0 overflow enable (tmr0ie bit)......................... 21 interrupts, flag bits interrupt-on change (rb7:rb4) flag (rbif bit) ........ 21 interrupt-on-change (rb7:rb4) flag (rbif bit)............................................. 21, 33, 100 rb0/int flag (intf bit) ............................................. 21 tmr0 overflow flag (tmr0if bit) ........................... 100 l load conditions................................................................ 123 loading of pc ..................................................................... 26 m master clear (mclr )............................................................ 8 mclr reset, normal operation..................... 93, 95, 96 mclr reset, sleep...................................... 93, 95, 96 operation and esd protection ................................... 94 mclr pin ........................................................................... 10 mclr /v pp pin ...................................................................... 8 memory organization ......................................................... 13 data memory .............................................................. 13 program memory ........................................................ 13 program memory and stack maps ............................. 13 microchip internet web site.............................................. 167 mplab asm30 assembler, linker, librarian ................... 114 mplab icd 2 in-circuit debugger ................................... 115
? 2007 microchip technology inc. ds21993c-page 163 pic16cr7x mplab ice 2000 high-performance universal in-circuit emulator .................................................... 115 mplab ice 4000 high-performance universal in-circuit emulator .................................................... 115 mplab integrated development environment software .. 113 mplab pm3 device programmer .................................... 115 mplink object linker/mplib object librarian ................ 114 o opcode field descriptions ............................................. 105 option_reg register ...................................................... 20 intedg bit ................................................................. 20 ps2:ps0 bits .............................................................. 20 psa bit........................................................................ 20 rbpu bit..................................................................... 20 t0cs bit...................................................................... 20 t0se bit...................................................................... 20 osc1/clki pin ............................................................... 8, 10 osc2/clko pin ............................................................. 8, 10 oscillator configuration....................................................... 89 oscillator configurations ..................................................... 91 crystal oscillator/ceramic resonators ....................... 91 hs ......................................................................... 91, 95 lp.......................................................................... 91, 95 rc................................................................... 91, 92, 95 xt ......................................................................... 91, 95 oscillator, wdt ................................................................. 101 p p (stop) bit........................................................................ 60 packaging ......................................................................... 149 marking ..................................................................... 149 pdip details.............................................................. 151 paging, program memory ................................................... 26 parallel slave port associated registers .................................................. 41 parallel slave port (psp).............................................. 36, 40 re0/rd /an5 pin................................................... 12, 39 re1/wr /an6 pin.................................................. 12, 39 re2/cs /an7 pin................................................... 12, 39 select (pspmode bit) ......................................... 36, 37 pcfg0 bit ........................................................................... 84 pcfg1 bit ........................................................................... 84 pcfg2 bit ........................................................................... 84 pcl register....................................................................... 26 pclath register ............................................................... 26 pcon register ............................................................. 25, 95 por bit ....................................................................... 25 picstart plus development programmer ..................... 116 pie1 register...................................................................... 22 pie2 register...................................................................... 24 pinout descriptions pic16cr73/pic16cr76........................................... 8?9 pic16cr74/pic16cr77....................................... 10?12 pir1 register...................................................................... 23 pir2 register...................................................................... 24 pmadr register................................................................. 29 pmadrh register .............................................................. 29 pop .................................................................................... 26 por. see power-on reset porta............................................................................ 8, 10 analog port pins ..................................................... 8, 10 associated registers .................................................. 32 porta register ......................................................... 31 ra4/t0cki pin........................................................ 8, 10 ra5/ss /an4 pin ..................................................... 8, 10 trisa register........................................................... 31 porta register ................................................................. 31 portb ........................................................................... 8, 11 associated registers.................................................. 34 portb register......................................................... 33 pull-up enable (rbpu bit).......................................... 20 rb0/int edge select (intedg bit) ........................... 20 rb0/int pin, external .................................... 8, 11, 100 rb7:rb4 interrupt-on-change ................................. 100 rb7:rb4 interrupt-on-change enable (rbie bit) .... 100 rb7:rb4 interrupt-on-change flag (rbif bit).............................................. 21, 33, 100 trisb register........................................................... 33 portb register ................................................................. 33 portc ........................................................................... 9, 11 associated registers.................................................. 35 portc register......................................................... 35 rc0/t1oso/t1cki pin.......................................... 9, 11 rc1/t1osi/ccp2 pin ............................................ 9, 11 rc2/ccp1 pin........................................................ 9, 11 rc3/sck/scl pin.................................................. 9, 11 rc4/sdi/sda pin................................................... 9, 11 rc5/sdo pin ......................................................... 9, 11 rc6/tx/ck pin................................................. 9, 11, 70 rc7/rx/dt pin .......................................... 9, 11, 70, 71 trisc register .......................................................... 35 portc register................................................................. 35 portd ............................................................................... 12 associated registers.................................................. 36 parallel slave port (psp) function............................. 36 portd register......................................................... 36 trisd register .......................................................... 36 portd register................................................................. 36 porte ............................................................................... 12 analog port pins................................................... 12, 39 associated registers.................................................. 39 input buffer full status (ibf bit)................................. 38 input buffer overflow (ibov bit)................................. 38 porte register......................................................... 37 psp mode select (pspmode bit)....................... 36, 37 re0/rd /an5 pin .................................................. 12, 39 re1/wr /an6 pin ................................................. 12, 39 re2/cs /an7 pin .................................................. 12, 39 trise register........................................................... 37 porte register ................................................................. 37 postscaler, wdt assignment (psa bit) ................................................. 20 rate select (ps2:ps0 bits) ........................................ 20 power-down mode. see sleep power-on reset (por)..................................... 89, 93, 95, 96 oscillator start-up timer (ost)............................ 89, 94 por status (por bit) ................................................ 25 power control (pcon) register................................. 95 power-down (pd bit) .................................................. 93 power-up timer (pwrt) ...................................... 89, 94 time-out (to bit).................................................. 19, 93 pr2 register ...................................................................... 51 prescaler, timer0 assignment (psa bit) ................................................. 20 rate select (ps2:ps0 bits) ........................................ 20 program counter reset conditions...................................................... 95 program memory ................................................................ 29 associated registers.................................................. 30 interrupt vector........................................................... 13 memory and stack maps ............................................ 13
pic18fxxxx ds21993c-page 164 ? 2007 microchip technology inc. operation during code protect................................... 30 organization................................................................ 13 paging ......................................................................... 26 pmadr register......................................................... 29 pmadrh register ...................................................... 29 reading rom ............................................................. 30 reading, pmadr register ......................................... 29 reading, pmadrh register....................................... 29 reading, pmcon1 register ....................................... 29 reading, pmdata register ....................................... 29 reading, pmdath register ....................................... 29 reset vector............................................................. 13 program verification.......................................................... 103 programming, device instructions .................................... 105 push .................................................................................. 26 r r/w bit .................................................................... 60, 66, 67 ra0/an0 pin ................................................................... 8, 10 ra1/an1 pin ................................................................... 8, 10 ra2/an2 pin ................................................................... 8, 10 ra3/an3/v ref pin.......................................................... 8, 10 ra4/t0cki pin................................................................ 8, 10 ra5/ss /an4 pin ............................................................. 8, 10 ram. see data memory rb0/int pin .................................................................... 8, 11 rb1 pin ........................................................................... 8, 11 rb2 pin ........................................................................... 8, 11 rb3 pin ........................................................................... 8, 11 rb4 pin ........................................................................... 8, 11 rb5 pin ........................................................................... 8, 11 rb6 pin ........................................................................... 8, 11 rb7 pin ........................................................................... 8, 11 rc0/t1oso/t1cki pin .................................................. 9, 11 rc1/t1osi/ccp2 pin..................................................... 9, 11 rc2/ccp1 pin ................................................................ 9, 11 rc3/sck/scl pin .......................................................... 9, 11 rc4/sdi/sda pin ........................................................... 9, 11 rc5/sdo pin .................................................................. 9, 11 rc6/tx/ck pin ............................................................... 9, 11 rc7/rx/dt pin ............................................................... 9, 11 rcsta register cren bit..................................................................... 70 oerr bit .................................................................... 70 spen bit ..................................................................... 69 sren bit..................................................................... 70 rd0/psp0 pin..................................................................... 12 rd1/psp1 pin..................................................................... 12 rd2/psp2 pin..................................................................... 12 rd3/psp3 pin..................................................................... 12 rd4/psp4 pin..................................................................... 12 rd5/psp5 pin..................................................................... 12 rd6/psp6 pin..................................................................... 12 rd7/psp7 pin..................................................................... 12 re0/rd /an5 pin................................................................. 12 re1/wr /an6 pin ................................................................ 12 re2/cs /an7 pin ................................................................. 12 reader response ............................................................. 168 read-modify-write operations.......................................... 105 receive overflow indicator bit (sspov)............................. 61 register file ........................................................................ 13 registers adcon0 (a/d control 0) ............................................ 83 adcon0 register....................................................... 83 adcon1 (a/d control 1) ............................................ 83 adcon1 register....................................................... 84 adres (a/d result)................................................... 83 ccp1con/ccp2con register ................................. 54 configuration word register ...................................... 90 initialization conditions (table).............................. 96?97 intcon (interrupt control)......................................... 21 intcon register........................................................ 21 option_reg ............................................................ 20 option_reg register........................................ 20, 44 pcon (power control) ............................................... 25 pcon register ........................................................... 25 pie1 (peripheral interrupt enable 1)........................... 22 pie1 register ............................................................. 22 pie2 (peripheral interrupt enable 2)........................... 24 pie2 register ............................................................. 24 pir1 (peripheral interrupt request 1) ........................ 23 pir1 register ............................................................. 23 pir2 (peripheral interrupt request 2) ........................ 24 pir2 register ............................................................. 24 pmcon1 (program memory control 1) register ....... 29 rcsta register ......................................................... 70 special function, summary.................................. 16?18 sspcon register ...................................................... 61 sspstat register ..................................................... 60 status register ....................................................... 19 t1con register ......................................................... 47 t2con register ......................................................... 52 trise register........................................................... 38 txsta register.......................................................... 69 reset.......................................................................... 89, 93 brown-out reset (bor). see brown-out reset (bor) mclr reset. see mclr power-on reset (por). see power-on reset (por) reset conditions for all registers ........................... 96 reset conditions for pcon register....................... 95 reset conditions for program counter .................... 95 reset conditions for status register ................... 95 reset wdt reset. see watchdog timer (wdt) revision history................................................................ 159 s s (start) bit ..................................................................... 60 sci. see usart scl..................................................................................... 65 serial communication interface. see usart sleep .................................................................. 89, 93, 102 smp bit ............................................................................... 60 software simulator (mplab sim) .................................... 114 special features of the cpu .............................................. 89 special function registers ..................................... 16, 16?18 speed, operating.................................................................. 1 spi mode ............................................................................ 59 associated registers .................................................. 64 serial clock (sck pin) ................................................ 59 serial data in (sdi pin)............................................... 59 serial data out (sdo pin) .......................................... 59 slave select................................................................ 59 ssp overview ra5/ss /an4 pin..................................................... 8, 10 rc3/sck/scl pin .................................................. 9, 11 rc4/sdi/sda pin ................................................... 9, 11 rc5/sdo pin.......................................................... 9, 11 ssp i 2 c operation.............................................................. 65 slave mode................................................................. 65 sspen bit........................................................................... 61
? 2007 microchip technology inc. ds21993c-page 165 pic16cr7x sspif bit............................................................................. 23 sspm<3:0> bits .................................................................. 61 sspov bit........................................................................... 61 stack ................................................................................... 26 overflows .................................................................... 26 underflow.................................................................... 26 status register dc bit.......................................................................... 19 irp bit......................................................................... 19 pd bit.......................................................................... 93 to bit.................................................................... 19, 93 z bit............................................................................. 19 synchronous serial port enable bit (sspen)..................... 61 synchronous serial port interrupt bit (sspif) .................... 23 synchronous serial port mode select bits (sspm<3:0>) ... 61 synchronous serial port. see ssp t t1ckps0 bit ....................................................................... 47 t1ckps1 bit ....................................................................... 47 t1oscen bit ...................................................................... 47 t1sync bit ......................................................................... 47 t2ckps0 bit ....................................................................... 52 t2ckps1 bit ....................................................................... 52 t ad ....................................................................................... 87 time-out sequence............................................................. 94 timer0 ................................................................................. 43 associated registers .................................................. 45 clock source edge select (t0se bit)......................... 20 clock source select (t0cs bit).................................. 20 external clock............................................................. 44 interrupt....................................................................... 43 overflow enable (tmr0ie bit).................................... 21 overflow flag (tmr0if bit) ...................................... 100 overflow interrupt ..................................................... 100 prescaler..................................................................... 45 ra4/t0cki pin, external clock .............................. 8, 10 t0cki.......................................................................... 44 timer1 ................................................................................. 47 associated registers .................................................. 50 asynchronous counter mode ..................................... 49 capacitor selection..................................................... 50 counter operation ...................................................... 48 operation in timer mode ............................................ 48 oscillator ..................................................................... 50 prescaler..................................................................... 50 rc0/t1oso/t1cki pin .......................................... 9, 11 rc1/t1osi/ccp2 pin............................................. 9, 11 resetting of timer1 registers .................................... 50 resetting timer1 using a ccp trigger output ........... 50 synchronized counter mode ...................................... 48 tmr1h register ......................................................... 49 tmr1l register.......................................................... 49 timer2 ................................................................................. 51 associated registers .................................................. 52 output ......................................................................... 51 postscaler ................................................................... 51 prescaler..................................................................... 51 prescaler and postscaler ............................................ 51 timing diagrams a/d conversion......................................................... 137 brown-out reset ....................................................... 126 capture/compare/pwm (ccp1 and ccp2) ............. 128 clkout and i/o....................................................... 125 external clock........................................................... 124 i 2 c bus data ............................................................. 133 i 2 c bus start/stop bits ............................................. 132 i 2 c reception (7-bit address)..................................... 67 i 2 c transmission (7-bit address) ............................... 67 parallel slave port .................................................... 129 parallel slave port read waveforms ......................... 41 parallel slave port write waveforms ......................... 41 power-up timer ........................................................ 126 pwm output ............................................................... 57 reset...................................................................... 126 slow rise time (mclr tied to v dd through rc network)......................................... 98 spi master mode (cke = 0, smp = 0) ..................... 130 spi master mode (cke = 1, smp = 1) ..................... 130 spi mode (master mode) ........................................... 63 spi mode (slave mode with cke = 0)........................ 63 spi mode (slave mode with cke = 1)........................ 64 spi slave mode (cke = 0) ....................................... 131 spi slave mode (cke = 1) ....................................... 131 start-up timer........................................................... 126 time-out sequence on power-up (mclr not tied to v dd ) case 1 ................................................................ 98 case 2 ................................................................ 98 time-out sequence on power-up (mclr tied to v dd through rc network)......... 97 timer0 ...................................................................... 127 timer1 ...................................................................... 127 usart asynchronous master transmission ............. 74 usart asynchronous master transmission (back to back) ................................................... 75 usart asynchronous reception .............................. 76 usart synchronous receive (master/slave) ......... 135 usart synchronous reception (master mode, sren) ........................................ 80 usart synchronous transmission ........................... 79 usart synchronous transmission (master/slave) .................................................. 135 usart synchronous transmission (through txen) ................................................. 79 wake-up from sleep via interrupt............................. 103 watchdog timer ....................................................... 126 timing parameter symbology .......................................... 123 timing requirements capture/compare/pwm (ccp1 and ccp2)............. 128 clkout and i/o ...................................................... 125 external clock .......................................................... 124 i 2 c bus data............................................................. 134 i2c bus start/stop bits............................................. 133 parallel slave port .................................................... 129 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset . 126 spi mode.................................................................. 132 timer0 and timer1 external clock ........................... 127 usart synchronous receive ................................. 135 usart synchronous transmission ......................... 135 tmr1cs bit ........................................................................ 47 tmr1on bit........................................................................ 47 tmr2on bit........................................................................ 52 toutps<3:0> bits ............................................................. 52 trisa register................................................................... 31 trisb register................................................................... 33 trisc register................................................................... 35 trisd register................................................................... 36
pic18fxxxx ds21993c-page 166 ? 2007 microchip technology inc. trise register ................................................................... 37 ibf bit ......................................................................... 38 ibov bit ...................................................................... 38 pspmode bit....................................................... 36, 37 txsta register sync bit..................................................................... 69 trmt bit..................................................................... 69 tx9 bit ........................................................................ 69 tx9d bit...................................................................... 69 txen bit ..................................................................... 69 u ua ....................................................................................... 60 universal synchronous asynchronous receiver transmitter. see usart update address bit, ua....................................................... 60 usart ................................................................................ 69 asynchronous mode ................................................... 73 asynchronous receiver .............................................. 75 asynchronous reception ............................................ 76 associated registers .......................................... 77 asynchronous transmission associated registers .......................................... 75 asynchronous transmitter .......................................... 73 baud rate generator (brg)....................................... 71 baud rate formula............................................. 71 baud rates, asynchronous mode (brgh = 0) .. 72 baud rates, asynchronous mode (brgh = 1) .. 72 sampling ............................................................. 71 mode select (sync bit) ............................................. 69 overrun error (oerr bit) ........................................... 70 rc6/tx/ck pin ....................................................... 9, 11 rc7/rx/dt pin ....................................................... 9, 11 serial port enable (spen bit)..................................... 69 single receive enable (sren bit) ............................. 70 synchronous master mode ......................................... 78 synchronous master reception .................................. 80 associated registers .......................................... 81 synchronous master transmission............................. 78 associated registers .......................................... 79 synchronous slave mode ........................................... 81 synchronous slave reception .................................... 82 associated registers .......................................... 82 synchronous slave transmission............................... 81 associated registers .......................................... 82 transmit data, 9th bit (tx9d)..................................... 69 transmit enable (txen bit)........................................ 69 transmit enable, nine-bit (tx9 bit) ............................ 69 transmit shift register status (trmt bit).................. 69 user code ......................................................................... 103 w wake-up from sleep......................................................... 89 interrupts .............................................................. 95, 96 mclr reset ............................................................... 96 wdt reset ................................................................. 96 wake-up from sleep ......................................................... 102 wake-up using interrupts ................................................. 102 watchdog timer (wdt).............................................. 89, 101 associated registers ................................................ 101 enable (wdte bit) ................................................... 101 postscaler. see postscaler, wdt programming considerations ................................... 101 rc oscillator............................................................. 101 time-out period ........................................................ 101 wdt reset, normal operation....................... 93, 95, 96 wdt reset, sleep........................................ 93, 95, 96 wcol bit ............................................................................ 61 write collision detect bit (wcol) ...................................... 61 www address ................................................................. 167 www, on-line support .................... ................................... 4
? 2007 microchip technology inc. advance information ds21993c-page 167 pic16cr7x the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic16cr7x ds21993c-page 168 advance information ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21993c pic16cr7x 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2007 microchip technology inc. advance information ds21993c-page 169 pic16cr7x product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16cr73 pic16cr74 pic16cr76 pic16cr77 temperature range: i= -40 c to +85 c (industrial) e= -40 c to+125 c (extended) package: pt = tqfp (thin quad flatpack) l=plcc so = soic sp = skinny plastic dip p=pdip pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: note1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel plcc, and tqfp packages only.
ds21993c-page 170 ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 12/08/06

▲Up To Search▲

Price & Availability of PIC16CR76IL

	To Download PIC16CR76IL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .